Mitac 8080 Service Manual - laptop schematics, notebook ...

SERVICE SERVICE MANUAL MANUAL FOR 

FOR 

8080 





BY: Sissel Diao 

TESTING TECHNOLOGY DEPARTMENT / TSSC 

May . 2003

Contents 

8080 N/B Maintenance 

1. Hardware Engineering Specification ………………………………………………………………… 

1.1 Introduction …………………………………………………………………………………………………………. 

1.2 Other Functions ……………………………………………………………………………………………………. 

1.3 Peripheral Components ……………………………………………………………………………………………. 

1.4 Power Management ………………………………………………………………………………………………… 

1.5 Appendix 1 : Intel 82801DBM ICH4-M GPIO Definitions ……………………………………………………… 

1.6 Appendix 2 : MiTAC 8080 Product Specification ………………………………………………………………… 

2. System View and Disassembly ………………………………………………………………………... 

2.1 System View ………………………………………………………………………………………………………… 

2.2 System Disassembly ………………………………………………………………………………………………… 

3. Definition & Location of Connectors / Switches …………………………………………………….. 

3.1 Mother Board ……………………………………………………………………………………………………….. 

3.2 DC to DC Board ……………………………………………………………………………………………………. 

4. Definition & Location of Major Components ……………………………………………………….. 

4.1 Mother Board ……………………………………………………………………………………………………….. 

5. Pin Description of Major Component …….…………………………………………………………. 

5.1 Intel Pentium M Processor ………………………………………………………………………………………… 

5.2 Intel 82855GM Memory Controller Hub (GMCH) ……………………………………………………………… 

4 

4 

32 

38 

41 

44 

45 

47 

47 

50 

74 

74 

77 

78 

78 

80 

80 

84 

1

Contents 


5.3 Intel 82801DBM I/O Controller Hub Mobile (ICH4-M) ………………………………………………………… 

6. System Block Diagram ……………………………………………………………………………….. 

7. Maintenance Diagnostics ……………………………………………………………………………… 

7.1 Introduction ………………………………………………………………………………………………………… 

7.2 Error Codes ………………………………………………………………………………………………………… 

7.3 Debug Tool ………………………………………………………………………………………………………….. 

8. Trouble Shooting ……………………………………………………………………………………… 

8.1 No Power ……………………………………………………………………………………………………………. 

8.2 No Display …………………………………………………………………………………………………………… 

8.3 VGA Controller Failure LCD No Display ………………………………………………………………………… 

8.4 External Monitor No Display ……………………………………………………………………………………… 

8.5 Memory Test Error ………………………………………………………………………………………………… 

8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………. 

8.7 Hard Driver Test Error ……………………………………………………………………………………………. 

8.8 CD-ROM Driver Test Error ………………………………………………………………………………………. 

8.9 USB Port Test Error ……………………………………………………………………………………………….. 

8.10 Audio Failure ……………………………………………………………………………………………………… 

8.11 LAN Test Error …………………………………………………………………………………………………… 

8.12 PC Card & Card Reader Socket Failure ………………………………………………………………………… 

90 

98 

99 

99 

100 

102 

103 

104 

109 

112 

114 

116 

118 

120 

122 

124 

126 

129 

131 

2

Contents 


8.13 IEEE1394 Failure ………….……………………………………………………………………………………… 

9. Spare Parts List ……………………………………………………………………………………….. 

10. System Exploded Views ……………………………………………………………………………… 

11. Circuit Diagram ……………………………………………………………………………………… 

12. Reference Material …………………………………………………………………………………... 

133 

135 

148 

149 

182 

3

1.1 Introduction 


1. Hardware Engineering Specification 

1.1.1 General Description 

This document describes the brief introduction for MiTAC 8080 portable notebook computer system. 

1.1.2 System Overview 

The MiTAC 8080 model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It 

can support Banias 1.3GHz ~ 1.7GHz. 

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard 

hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface 

(ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can 

be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system 

status, such as AC Power indicator, Battery Power indicator, Battery status indicator, CD-ROM, HDD, NUM LOCK, 

CAP LOCK, SCROLL LOCK, RF on/off status and Card Reader indicator. It also equipped with LAN, 56K Fax 

MODEM, 3 USB port, 3D stereo audio functions, S-Video and audio line out(S/PDIF), external microphone and an 

optional finger printer in function. 

The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDR-SDRAM. 

4


The Montara-GM GMCH Host Memory Controller integrates a high performance host interface for Intel Banias 

processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port 

(DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M. 

The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller 

with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, and Intel Hub 

interface technology. 

The VIA VT6105LOM “Rhine III” Ethernet controller is a cutting edge, feature-rich, and cost-competitive single 

ASIC chip solution for PC “Lan On Motherboard” applications or Low Cost NIC applications. The 6105LOM eases 

server processor utilization by optimizing throughput between NIC and PCI bus allowing data transfers of up to at 

200Mbps in full duplex mode, without using the system CPU. The VT6105LOM contains advanced power 

management feature for low power consumption including Wake On LAN (WOL) and is implemented using a low 

power 0.22 micron design. 

The VT6307L is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It 

implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 

1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data 

transfer via a 32-bit bus master PCEI host bus interface. The VT6307L supports 100, 200 and 400 Mbit/sec 

transmission via an integrated 2-port PHY. The VT6307L services two types of data packets: asynchronous and 

isochronous(real time). The 1394 link core performs arbitration requesting, packet generation and checking, and bus 

cycle master operations. It also has root node capability and performs retry operations. 

The ENE CB710 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also PCI 

interface smart card and MS/SD/SM flash card reader. The CB710 provide one Cardbus slot and all reader interface 

may operate simultaneously. 

5


The NS PC87393 LPC Super I/O device is targeted for a wide range of portable applications. PC99 and ACPI 

compliant, it also incorporates: a Floppy Disk Controller (FDC), two enhanced Serial Ports (UARTs), one with Fast 

Infrared (FIR, IrDA 1.1 compliant), General-Purpose Input/Output (GPIO) support for a total of 32 ports, Interrupt 

Serializer for Parallel IRQs and an enhanced WATCHDOG timer. 

The NS PC87393 Super I/O controller integrates the standard PC I/O functions: LPC bus interface, X-Bus Extension 

for read and write operations, floppy disk interface and one EPP/ECP capable parallel port. Like all LPC Super I/O 

devices, the PC87393 offers a single-chip solution to the most commonly used PC I/O peripherals to provide for the 

increasing number of multimedia application. 

The STAC9750 is a 2 channel, 20-Bit DAC and 20-Bit ADC, full duplex AC’97 2.2 compatible stereo audio CODEC 

designed for PC multimedia systems, including soft/host audio and riser card base design. The STAC9750 supports 

with independent variable hardware sampling rates. The STAC9750 CODEC provides two pairs of stereo outputs with 

independent volume control, a mono output, a headphone output, and multiple stereo and mono inputs, alone with 

flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The STAC9750 also 

support an AC’97 2.2 compliant S/PDIF out functions which allows easy connection from the PC to consumer 

electronic products. 

The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and transmits 

data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable 

voltage data port which supports five different data format including RGB and YcrCb. The TV-Out processor will 

perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the 

NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text 

display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and horizontal underscan 

capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. 

6


Support is provided for Macrovision and RGB bypass mode which enable driving a VGA CRT with the input data. 

The H8/F3437 is a high performance microcontroller with a fast H8/300 CPU core and a set of on-chip supporting 

functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication 

interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions 

needed in control system configurations, so that compact, high performance systems can be implemented easily. 

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME, 

Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering 

IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power 

shutdown. 

Following chapters will have more detail description for each individual sub-systems and functions. 

System parts 

CPU : Intel Banias processors in Micro-FCPGA package. 

Synthesizer : ICS950810. 

North Bridge : Montara-GM GMCH. 

South Bridge: ICH4-M 

TV-OUT : CH7011A 

Super I/O controller : NS PC87393 

Keyboard System : Hitachi H8/F3437 Universal Controller 

FAX/MODEM : Billonton MDC56S-I 56Kbps Fax Modem 

7

LAN single chip : VT6105LOM 

PCMCIA controller : ENE CB710 

AC’97 Codec : STAC9750 

Thermal sensor : ADM1021A 

System Flash Memory (BIOS) 

1.1.2.1 CPU Module 


Intel Banias Processors with 478 pins Micro-FCPGA package. 

The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyper-pipelined 

technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution, 

advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). 

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications 

including 3-D graphics, video decoding/encoding, and speech recognition. 

Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four 

times per bus clock. 

Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and 

frequency between two performance modes. 

8

1.1.2.2 Synthesizer 

System frequency synthesizer: ICS950810 


Programmable output frequency, divider ratios, output rise/fall time, output skew. 

Programmable spread percentage for EMI control. 

Watchdog timer technology to reset system if system malfunctions. 

Programmable watchdog safe frequency. 

Support I2C Index read/write and block read/write operations. 

1.1.2.3 Montara-GM GMCH IGUI 3D Graphic DDR/SDR Chipset 

Montara-GM GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel Banias 

processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, 

and Intel® I/O Hub architecture INTEL 82801DBM ICH4-M. 

Montara-GM GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated 

on-die termination to support Intel Banias processors. Montara-GM GMCH provides a 12-deep In-Order-Queue to 

support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video 

Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Banias series based 

PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth 

demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition 

to integrated GUI, Montara-GM GMCH also can support external AGP slot with AGP 1X/2X/4X capability and Fast 

Write Transactions. 

9


A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara-GM GMCH and 

Intel 82801DBM ICH4-M together. Intel® I/O Hub architecture is developed into three layers, the Multi-threaded 

I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters 

to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in Intel 82801DBM 

ICH4-M to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GM 

GMCH, and the Multi-threaded I/O Link Encoder/Decoder in Montara-GM GMCH to transfer data w/ 533 MB/s 

from/to Multi-threaded I/O Link layer to/from Intel 82801DBM ICH4-M. 

An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data 

transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP 

master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the 

CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GM GMCH adopts 

the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing 

the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB. 

Features : 

Processor/Host Bus Support 

-Intel ® Banias processor 

- 2X Address, 4X data 

- Support host bus Dynamic Bus Inversion (DBI) 

- Supports system bus at 400MT/s (100 MHz) 

- Supports 64-bit host bus addressing 

- 8-deep In-Order-Queue 

- AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation (1.05V) 

- Supports Enhanced Intel ® SpeedStepTM Technology (EIST) and Geyserville III 

10


- Support for DPWR# signal to Banias processor for PSB power management 

Memory System 

- Directly supports one DDR channel, 64-bts wide (72-b with ECC). 

- Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated) 

with unbuffered PC1600/PC2100 DDR(with ECC). 

- Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x 16 devices. 

- All supported devices have 4 banks. 

- Supports up to 16 simultaneous open pages. 

- Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row. 

- UMA support only. 

System interrupt 

- Supports 8259 and Processor System Bus interrupt delivery mechanism 

- Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface 

- MSI sent to the CPU through the system Bus 

- From IOxAPIC in ICH4-M 

- Provides redirection for upstream interrupts to the System Bus 

- Video Stream Decoder 

- Improved HW Motion Compensation for MPEG2 

- All format decoder (18 ATSC formats) supported 

- Dynamic Bob and Weave support for Video Streams 

- Software DVD at 60 fields/second and 30 frames/second full screen 

- Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization 

11


- Video Overlay 

- Single high quality scalable overlay and second Sprite to support second overlay 

- Multiple overlay functionality provided via Arithmetic Stretch Blt 

- Direct YUV from Overlay to TV-out 

- Independent Gamma Correction 

- Independent Brightness / Contrast / Saturation 

- Independent Tint / Hue support 

- Destination Color keying 

- Source Chromakeying 

- Maximum source resolution of 1920x1080 pixels 

- Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or 1280x 

1024@ 85 Hz 

Display 

- Analog Display Support 

- 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor up to 1800 

x1350@ 85 Hz. 

- Accompanying I2C and DDC channels provided through multiplexed interface Hot-plug and display support 

- Dual independent pipe with single display support Simultaneous: Same images and native display timings on 

each display device 

- DVO (DVOB) support 

- Digital video out port DVOB with 165-MHz dot clock on 12-bit interface 

-- Variety of DVO devices channel 

-- Compliant with DVI Specification 1.0, thereby providing support for a flat panel up to 2048x1536 pixel 

resolution, or digital CRT up to 1920x1080 pixel resolution 

12


- Dedicated LFP (local flat panel) interface 

-- Single or dual channel LVDS panel support up to SXGA+ panel resolution with frequency range from 

25MHz to 112MHz per channel 

-- SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC clock 

-- Supports data format of 18 bpp 

-- Direct YUV from Overlay to TV-out 

-- LCD panel power sequencing compliant with SPWG timing specification 

-- Compliant with ANSI/TIA/EIA –644-1995 spec 

-- Integrated PWM interface for LCD backlight inverter control 

-- Bi-linear Panel fitting 

- Tri-view support through LFP interface, DVO ports and CRT 

- Internal Graphics Features 

- Core Frequency 

-- Display Core frequency of 133MHz 

-- Render Core frequency of 133MHz 

- 2D Graphics Engine 

- Optimized 128 bit BLT engine 

- Ten programmable and predefined monochrome patterns 

- Alpha Stretch Blt (via 3D pipeline) 

- Anti-aliased lines 

- Hardware-based BLT Clipping & Scissoring 

- 32-bit Alpha Blended cursor 

- Programmable 64*64 3-color Transparent cursor 

- Color Space Conversion 

- 3 Operand Raster BLTs 

13


- 8-bit, 16-bit, and 32-bit color 

- ROP support 

- DIB translation and Linear/Title addressing 

- 3D Graphics Engine 

- 3D Setup and Render Engine 

- Viewpoint Transform and Perspective Divide 

- Triangle Lists, Strips and Fans support 

- Indexed Vertex and Flexible Vertex formats 

- Pixel accurate Fast Scissoring and Clipping operation 

- Back-face Culling support 

- DirectXTM and OGL Pixelization rules 

- Anti-Aliased Lines support 

- Sprite Points support 

- Zone Rendering 

- Provides the highest sustained fill rate performance in 32-bit color and 24-bit W mode 

- High quality performance Texture Engine 

- 266 MegaTexel/speak performance 

- Per Pixel Perspective corrected Texture Mapping 

- Single Pass Texture Composting (Multi-Texture) at rate 

- Enhanced Texture Blending functions 

- Twelve Level of Detail MIP Map Sizes from 1x1 to 2Kx2K 

- Numerous Texture formats including 32-bit RGBA 

- Alpha and Luminance Maps 

- Texture Chromakeying 

14


- Bilinear, Trilinear, Anisotropic MIP-Mapped Filtering 

- Cubic Environment Reflection Mapping 

- Embossed Bump-mapping 

- DXTn Texture Decompression 

- 3D Graphics Rasterrization enhancements 

- One Pixel per Clock 

- Flat and Gouraud Shading 

- Color Alpha Blending for Transparency 

- Vertex and Programmable Pixel Fog and Atmospheric effects 

- Color Specular Lighting 

- Vertex and Programmable Pixel Fog and Atmospheric effects 

- Z Bais support 

-Dithering 

- Line and Full-Scence Anti-Aliasing 

- 16 and 24-bit Z Buffering 

- 16 and 24-bit W Buffering 

- 8-bit Stencil Buffering 

- Double and Triple Render Buffer support 

- 16 and 32 –bit color 

- Destination Alpha 

- Vertex Cache 

- Maximum 3D resolution of 1600x1200 x32 bpp at 85 Hz 

- Optimal 3D resolution supported 

- Fast Clear support 

15

HUB Interface for ICH4 


- 266 MB/s point to point hub interface to ICH4-M 

- 66-M Hz base clock 

- Supports the following traffic types to the ICH4-M 

- Hub interface-to DRAM 

- CPU-to-Hub interface 

- Messaging 

- MSI interrupt messages 

- Power Management state change 

- SMI, SCI, and SERR error indication 

- Power Management 

-- SMRAM space remapping to A0000h (128-KB) 

-- Supports extended SMRAM space above 256- MB ,additional 1 MB TSEG from top of Memory, cacheable 

(cacheability controlled by CPU) 

-- APM rev 1.2 compliant power management 

-- Supports Suspend to System Memory(S3),Suspend to Disk(S4) and Hard Off/Total Reboot(S5) 

-- ACPI 1.0b,2.0 Support 

16


1.1.2.4 I/O Controller Hub : Intel 82801DBM 

The Intel 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller with 

AC 97 Interface, the IDE Master/Slave controllers, and Intel® I/O Hub architecture. The PCI to LPC Bridge, I/O 

Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management functionalities are 

integrated as well. 

The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers 

with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB devices as well as 

over current detection are also implemented. 

The Integrated AC97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and HSP v.90 

modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting 

multiple audio codecs with one separate modem codec. 

The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode transfers 

up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that 

sustain the high data transfer rate in the multitasking environment. 

Intel 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the 

legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three 8254 

compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse interface(not 

use in MiTAC 8080 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59 compatible Interrupt 

controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB interrupt delivery modes is 

supported. 

17


The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2 

compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and 

power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for 

specific application. In addition, the Intel 82801DBM ICH4-M supports Deeper Sleep power state for Intel Mobile 

processor. 

A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara and Intel 82801DBM 

ICH4-M Hub interface together. Intel® I/O Hub architecture is developed 

Features : 

PCI Bus Interface 

Supports PCI Revision 2.2 Specification at 33 MHz 

133 MB/sec maximum throughput 

Supports up to six master devices on PCI 

One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller) 

Support for 44-bit addressing on PCI using DAC protocol Integrated LAN Controller 

WfM 2.0 and IEEE 802.3 compliant 

LAN Connect Interface (LCI) 

10/100 Mbit/sec Ethernet support_ Integrated IDE Controller 

Supports “Native Mode” register and interrupts 

Independent timing of up to 4 drives, with separate primary and secondary IDE cable connections 

18

Ultra ATA/100/66/33, BMIDE and PIO modes 

Tri-state modes to enable swap bay 

USB 


Includes three UHCI host controllers that support six external ports 

New: Includes one EHCI high-speed USB 2.0 Host Controller that supports all six ports 

New: Supports a USB 2.0 high-speed debug port 

Supports wake-up from sleeping states S1–S5 

Supports legacy keyboard/mouse software AC-Link for Audio and Telephony CODECs 

Supports AC ’97 2.3 

New: Third AC_SDATA_IN line for three codec support 

New: Independent bus master logic for seven channels (PCM In/Out, Mic 1 input, Mic 2 input, modem in/out, 

S/PDIF out) 

Separate independent PCI functions for audio and modem 

Support for up to six channels of PCM audio output (full AC3 decode) 

Supports wake-up events Interrupt Controller 

Support up to eight PCI interrupt pins 

Supports PCI 2.2 message signaled interrupts 

Two cascaded 82C59 with 15 interrupts 

Integrated I/O APIC capability with 24 interrupts 

19

Supports serial interrupt protocol 


Supports processor system bus interrupt delivery New: 1.5 V operation with 3.3 V I/O 

5 V tolerant buffers on IDE, PCI, USB over current and legacy signals Timers Based on 82C54 

System timer, refresh request, speaker tone output Power Management Logic 

ACPI 2.0 compliant 

ACPI-defined power states (C1–C2, S3–S5 ) 

Supports Desktop S1 state (like C2 state, only STPCLK# active) 

ACPI power management timer 

PCI PME# support 

SMI# generation 

All registers readable/restorable for proper resume from 0 V suspend states External Glue Integration 

Integrated pull-up, pull-down and series termination resistors on IDE, processor interface 

Integrated Pull-down and Series resistors on USB Enhanced Hub Interface Buffers Improve Routing flexibility 

(Not available with all Memory Controller Hubs) 

20

1.1.2.5 CH7011A 


The CH7011 is a Display controller device which accepts a digital graphics input signal, and encodes and transmits 

data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable 

voltage data port which supports five different data formats including RGB and YCrCb.The TV-Out processor will 

perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the 

NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text 

display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan 

capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. 

Support is provided for Macrovision and RGB bypass mode which enables driving a VGA CRT with the input data. 

Features : 

TV output supporting up to 1024x768 graphics resolutions 

Macrovision 7.X copy protection support 

Programmable digital interface supports RGB and YCrCb 

True scale rendering engine supports underscan in all TV output resolutions 

Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering 

Support for all NTSC and PAL formats 

Provides CVBS, S-Video and SCART (RGB) outputs 

TV connection detect 

Programmable power management 

10-bit video DAC outputs 

21

Fully programmable through serial port 

Complete Windows and DOS driver support 

Low voltage interface support to graphics device 

1.1.2.6 Super I/O_NS PC87393 


National Semiconductor’s PC8739x family of LPC Super I/O devices is targeted for a wide range of portable 

applications. PC99 and ACPI compliant, the PC8739x family features an X-Bus Extension for read and write 

operations over the X-Bus, a full IEEE 1284 Parallel Port with a Parallel Port Multiplexer (PPM) for external Floppy 

Disk Drive (FDD) support, a Musical Instrument Digital Interface (MIDI) port, and a Game port. Like all National 

LPC Super I/O devices, the PC8739x offers a single-chip solution to the most commonly used PC I/O peripherals. 

The PC8739x family also incorporates: a Floppy Disk Controller (FDC), two enhanced Serial Ports (UARTs), one 

with Fast Infrared (FIR, IrDA 1.1 compliant), General-Purpose Input/Output (GPIO) support for a total of 32 ports, 

Interrupt Serializer for Parallel IRQs and an enhanced WATCH DOG timer. 

22


1.1.2.7 Keyboard controller Hitachi H8/3437 

The H8/3437 Series is a series of high-performance micro-controllers with a fast H8/300 CPU core and a set of onchip 

supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial 

communication interface, optional I2C bus interface, host interface, A/D converter, D/A converter, I/O ports, and 

other functions needed in control system configurations, so that compact, high-performance systems can be 

implemented easily. The series includes the H8/3437 with 60kbyte ROM and 2kbyte RAM, the H8/3436 with 48kbyte 

ROM and 2kbyte RAM, and the H8/3434 with 32kbyte ROM and 1kbyte RAM. 

The H8/3437, H8/3436, and H8/3434 are available in mask-ROM versions. The H8/3437 and H8/3434 are also 

available in ZTAT*1 (zero turn-around time) versions, providing a quick and flexible response to conditions from 

ramp-up through full-scale volume production, even for applications with frequently-changing specifications. In 

addition, the H8/3434 and H8/3437 have F-ZTAT*2 (flexible-ZTAT) versions with on-board programmability. 

1.1.2.8 Fast Ethernet Controller VT6105LOM 

The VIA Rhine III VT6105LOM is a 10/100Mbps Fast Ethernet controller designed to provide system designers an 

easy to integrate single chip solution, with advanced management and power conservation features. Featuring a 3-in-1 

design the VIA VT6105LOM integrates the physical, media, and management layers into a single chip. 

Features : 

Single chip full/half duplex 10/100Mbps Fast Ethernet Management Controller 

IEEE 802.3/802.3u 10BASE-T and 100BASE-T Compatible 

23

32bit PCI Bus-Master Interface 


VIA Rhine based CSR definition provides efficiency PCI bus-mastering 

Low power 100base-TX transceiver embedded Support 10Mbps and 100Mbps N-way Auto-negotiation operation 

Support Auto-MDIX function 

Enhancement MAC functions for 802.3 networking 802.1 Priority Transmit Maximum eight priority queues by 

drivers programmable 802.1q Multiple VLAN support VLAN long frames support (1518+4bytes) VLAN tag 

auto inserting and extracting on TX and RX side (VT6105LOM) NIC auto filtering on VLAN ID optional 

(VT6105LOM) 

IP header Checksum Offload supporting for Ipv4 frames. Support both of TCP and UDP protocol (VT6105LOM) 

Support Physical, Broadcast, and Multicast addresses filtering using both hashing table look-up and perfect-match 

mechanisms (VT6105LOM) 

12 sets hardware 16 bit MIB counters (VT6105LOM) 

Fiber Optic network support (VT6105LOM) 

WFM 2.0 (VT6105LOM) 

DMI 2.0 (H/W) 

IO 3.3v with PCI bus 5V tolerant / Core 2.5v power, using low power 0.22um TSMC CMOS process, 128pin 

PQFP package. 

24

1.1.2.9 Fax/Modem module 

Made by Billionton Computer corporation 

Integrated PCI v2.2 Interface 

Host-based ITU V.70 DSVD. 

Operation support: Windows 95/NT/ME/2000 


K56flex for internet connection rates approaching 56kbits/s. 

Data Modes capabilities 

On Chip PnP Logic 

ACPI support “On Now” 

Support “Call ID” 

PC 97 Compliant – Unimodem/V Compliant 

Low Power Consumption 

Operation Voltage 3.3V 

25


1.1.2.10 PCMCIA controller_ ENE CB710 + ENE CP2211 

CB710 

It’s function as a signal-slot PCI-to-Cardbus bridge and also PCI-interface smart card and MS/SD/SM flash card 

readers. 

Features : 

One Cardbus slot and all reader interfaces may operate simultaneously. 

- 280pin LPFQ or 209pin-ball LFBGA package. 

- 3.3V core operation with 5V tolerant I/O pads. 

- Compliant with PCI 2.2, ACPI 1.0, ect. 

- One traffic LED pin for each reader interface. 

Cardbus Controller: 

- working with ENE CP2211 Cardbus power switch. 

- Compliant with PC Card Standard 8.0. 

- Configurable interrupts and miscellaneous control logic. 

Smart Card Reader: 

- Compliant with PC/SC Specification 1.0. 

- Support ISO7816 T=0 and T=1 protocols and 3V/5V cards. 

Secure Digital (SD) Reader: 

- Compliant with SD Memory Card Specification Version 1.0. 

- Max 10MBps data rate with 16-byte data buffer and optional clock source. 

26


- Support 4-bit data lines, write protect switch, card detection by DAT3 or a dedicated switch. 

Memory Stick (MS) Reader: 

- Compliant with Memory Stick Standard Format Specification Version 1.3 

- Max 2.5MBps data rate with 16-byte data buffer and optional clock source. 

Smart Media (SM) Reader: 

- Compliant with SmartMedia Standard 2000 and SmartMedia Interface Library (SMIL) version 1.0. 

- Support 5V and 3V SmartMedia cards. 

- Support Hardware ECC (1-bit correction and 2-bits detection) 

CP2211 (Power Switch) 

Fully integrated V CC and V PP switching 

Low r DS(ON) : 90-mΩ 5V and 3.3V V CC Switches 

Compatible with industry standard controllers 

12V supply not required unless the PC Card uses 12V for flash programming or other applications 

3.3V low voltage mode 

Short-circuit and thermal protection 

Compatible with 3.3V, 5V, and 12V PC Cards 

27

1.1.2.11 AC”97 Codec _ STAC9750 


High performance CODEC with high S/N ratio (>90 dB). 

Compliant with AC’97 2.2 specifications 

20-bit stereo Digital-to-Analog Converter with variable sampling rate. 

20-bit stereo Analog-to-Digital Converter with variable sampling rate. 

4 analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, VIDEO, AUX. 

2 analog line-level mono inputs: PC_BEEP, PHONE_IN. 

Mono output with 5-bit volume control. 

Stereo output with 5-bit volume control. 

2 MIC inputs are software selectable. 

Power management capabilities. 

3D Stereo Enhancement 

Embedded 50mW/20 ohm at LINE output. 

External amplifier power down capability. 

Digital S/PDIF output. 

Built in 14.318M 24.576MHz PLL to save external 24.576MHz crystal 

Supports 2 general-purpose I/O pins. 

Power supply: Digital: 3.3V; Analog: 5V/3.3V 

Standard 48-Pin LQFP Package 

28

1.1.2.12 Thermal Sensor_ ADM1021A 

On-Chip and Remote Temperature Sensing 

No Calibration Necessary 

1_C Accuracy for On-Chip Sensor 

3_C Accuracy for Remote Sensor 

Programmable Over/Under Temperature Limits 

Programmable Conversion Rate 

2-Wire SMBus Serial Interface 

Supports System Management Bus (SMBus) Alert 

200 _A Max Operating Current 

1 _A Standby Current 

3 V to 5.5 V Supply 

Small 16-Lead QSOP Package 


29

1.1.2.13 System Flash Memory (BIOS) 

4M bit Flash memory 

Flashed by 5V only 


User can upgrade the system BIOS in the future just running flash program. 

1.1.2.14 IEEE1394a Controller VT6307L 

The VIA Fire IIM VT6307 is a single-chip, low power 2-port IEEE 1394 host controller providing PC systems with 

high speed, flexible connectivity to a wide range of peripherals and consumer electronics. Supporting the latest high 

speed IEEE 1394a standards, the VIA VT6307 can detect connected device types and automatically configure data 

speeds to 100, 200, or 400 Mbps, transmitting both asynchronous and isochronous (real-time) data packets. 

Features : 

Single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000 Embedded 1394 Link core 

- Dual Buffer mode enhancements 

- Skip Processing enhancements 

- Block Read Request handling 

- 32 bit CRC generator and checker for receive and transmit data 

Integrated 400Mbps 2-port PHY 

- Supports two 1394a fully compliant cable ports at 100/200/400Mbps 

- Supports IEEE 1394-1995 Standard for High Performance Serial Bus 1.0 and 1394a P2000 

30


- Full 1394a P2000 support 

- Logic performs bus initialization and arbitration functions 

- 2KV ESD protection 

32-Bit Power-Managed PCI Bus-Interface 

- Compliant with PCI specification v2.2 

- Supports CardBus interface 

Supports I2C EEPROM and 4-Wire Serial ROM with GUID PROM Shadow to EEPROM 

OHCI Compliant Programming Interface 

Pin Compatible with VIA VT6306 1394a PCI Host Controller 

3.3V Power Supply with 5V Tolerant Inputs 

0.30 micron low power CMOS process 

128-Pin, LQFP Package 

PCB reference designs & schematics available 

31

1.2 Other Functions 

1.2.1 Hot Key Function 

Keys 

combination 

Fn + F1 

Fn + F2 

Fn + F3 

Fn + F4 

Fn + F5 

Fn + F6 

Fn + F7 

Fn + F8 

Fn + F9 

Fn + F10 

Fn + F11 

Fn + F12 

Reserve 

Reserve 

Volume Up 

Brightness Up 

Reserve 

Reserve 

Panel Off/On 


Feature 

Volume Down 

LCD/External CRT 

Switching 

Brightness Down 

Battery beep enable/disable 

Suspend to DRAM/HDD 

Rotate display mode in LCD only, CRT only and simultaneously 

display. 

Decreases the LCD brightness 

Increases the LCD brightness 

Battery low beep sound enable/disable 

Toggle Panel Off/On 

Meaning 

Force the computer into either Suspend to HDD or Suspend to 

RAM mode. 

32


1.2.2 Power On/Off/Suspend/Resume Button 

1.2.2.1 APM Mode 

At APM mode, Power button is on/off system power. 

1.2.2.2 ACPI Mode 

At ACPI mode. Power button behavior was set by windows power management control panel. 

You could set “standby” , “power off” or “hibernate”(must enable hibernate function in power management) to power 

button function. Continue pushing power button over 4 seconds will force system off at ACPI mode. 

1.2.3 Cover Switch 

System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the 

usage time when user closes the notebook cover. 

At ACPI mode there are four functions to be chosen at windows power management control panel. 

1. None 

2. Standby 

3. Off 

4. Hibernate (must enable hibernate function in power management) 

33

1.2.4 LED Indicators 


System has eight status LED indicators to display system activity, which include three at front side and five above 

keyboard. 

1.2.4.1 Three LED indicators on LCD panel: 

From left to right that indicate: AC POWER, BATTERY POWER and BATTERY STATUS. 

AC POWER : This LED lights green when the notebook is being powered by AC, and flash (on 1 second, off 1 

second) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by 

batteries. 

BATTERY POWER : This LED lights green when the notebook is being powered by Battery , and flash (on 1 

second, off 1 second) when Suspend to DRAM is active using Battery power. The LED is off when the notebook is 

off or powered by batteries, or when Suspend to Disk. 

BATTERY STATUS : During normal operation, this LED stays off as long as the battery is charged. When the 

battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC 

is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being 

charged. 

34

1.2.4.2 Five LED indicators at front side: 


From left to right that indicates CD-ROM/HARD DISK DRIVE, NUM LOCK, CAPS LOCK and SCROLL LOCK. 

1.2.5 Battery status 

1.2.5.1 Battery Warning 

System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his data 

before battery dead. Also, this function protects system from mal-function while battery capacity is low. 

Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds. 

System will Suspend to HDD after 2 Minutes to protect users data. 

1.2.5.2 Battery Low State 

After Battery Warning State, and battery capacity is below 4%, system will generate beep for twice per second. 

1.2.5.3 Battery Dead State 

When the battery voltage level reaches 7.6 volts, system will shut down automatically in order to extend the battery 

packs' life. 

35

1.2.6 Fan Power On/Off Management 


FAN is controlled by H8 embedded controller using ADM1021A to sense CPU temperature and PWM control fan 

speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed. 

1.2.7 CMOS Battery 

CR2032 3V 220mAh lithium battery. 

When AC in or system main battery inside, CMOS battery will consume no power. AC or main battery not exist, 

CMOS battery life at less (220mAh/5.8uA) 4 years. Battery was put in battery holder, can be replaced. 

36

1.2.8 I/O Port 

One Power Supply Jack. 

One External CRT Connector For CRT Display 

One S-Video TV Output Connector 

Supports three USB2.0 port for all USB devices. 

One MODEM RJ-11 phone jack for PSTN line 

One RJ-45 for LAN. 

Microphone Input Jack. 

S/PIDF out Jack 


One CardBus Sockets for one type II PC card extension 

Two Card Reader Sockets for SM/MMC/SD/MS 

One IR port (use SHARP GP2W1001YP) 

One IEEE 1394a port for all firewire devices 

37

1.3 Peripheral Components 

1.3.1 LCD Panel 

1 st Source QDI 14.1” TFT: QD141X1LH03-MP01 

2 nd Source: Chi-Mei 14.1 TFT : N141X6-L0 

1.3.2 Ext. Floppy Disk Drive 


External USB 3.5” 1.44MB /1.2 MB/720KB FDD (Option) 

1 st Source :Mitsumi D353FUE 

2 nd Source :NEC UF0002 

1.3.3 HDD 

Fujitsu 20GB: MHR2020AT / 30GB: MHR2030AT/ 40GB : MHR2040AT 

Hitachi 20 GB: DK23DA-20F / 30GB DK23DA-30F/ 40GB DK23DA-40F 

1.3.4 Keyboard 

JME 19mm pitch/3.0mm stroke 

38

1.3.5 DVD ROM Drive 

1 st source :TEAC DV-28E-B93 

2 nd source: QSI SDR-083 

1.3.6 COMBO Drive 

1 st source : KME UJDA730-MT-A 

2 nd source : QSI SBW-161(16X Combo) 

3 rd source : NEC CB2100A 


1.3.7 Track Pad : Synaptics TM41PUM311-2 

Accurate positioning 

Low fatigue pointing action 

Low profile 

No moving part, high reliability 

Low power consumption 

Environmentally sealed 

Compact size 

39

Software configurable 

Low weight 

Operating temperature: 0 to 60 degree C 


Operating humidity : 5%-95% relative humidity, non condensing 

Storage temperature: -40 to +65 degree C 

ESD: 15KV applied to front surface SEE ESD Testing specification PN 520-000270-01 

Power supply voltage : 5.0Voltage ± 10% 

Power supply current : 4.0mA max operating 

1.3.8 Fan 

HY45J05-001 

40

1.4 Power Management 


The MiTAC 8080 system has built in several power saving modes to prolong the battery usage for mobile purpose. 

User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by 

pressing F2 key). Following are the descriptions of the power management modes supported. 

1.4.1 System Management Mode 

1.4.1.1 Full On Mode 

In this mode, each devices is running with the maximal speed. CPU clock is up to its maximum. 

1.4.1.2 Doze Mode 

In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can 

save battery power without loosing much computing capability. 

The CPU power consumption and temperature is lower in this mode. 

41

1.4.1.3 Standby Mode 


For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device: 

CPU: Stop grant 

LCD: backlight off 

HDD: spin down 

1.4.1.4 Suspend to DRAM and HDD 

The most chipset of the system is entering power down mode for more power saving. In this mode, the following is 

the status of each device: 

Suspend to DRAM 

- CPU: off 

- NB: Partial off 

- VGA: Suspend 

- PCMCIA: Suspend 

- Audio: off 

- SDRAM: self Refresh 

Suspend to HD 

- All devices are stopped clock and power-down 

- System status is saved in HDD 

- All system status will be restored when powered on again 

42


1.4.2 Other Power Management Functions 

1.4.2.1 HDD & Video Access 

System has the ability to monitor video and hard disk activity. User can enable monitoring video and/or hard disk 

individually. When there is no video and/or hard disk activity, system will enter next PMU state depending on the 

application. When the VGA activity monitoring is enabled, the performance of the system will have some impact. 

43


1.5 Appendix 1: Intel 82801DBM ICH4-M GPIO Definitions 

Pin Name 

GPIO0 

GPIO1 

GPIO2 

GPIO3 

GPIO4 

GPIO5 

GPIO6 

GPIO7 

GPIO8 

GPIO11 

GPIO12 

GPIO13 

GPIO16 

GPIO17 

GPIO18 

GPIO19 

GPIO20 

GPIO21 

GPIO22 

MUX Function 

CRT_IN# 

X 

INT_PIRQE# 

INT_PIRQF# 

INT_PIRQG# 

X 

AGP_BUSY# 

KB_US/JP# 

EXTSMI# 

SMBALERT# 

SCI# 

WAKE_UP# 

SIDE_OFF# 

PIDE_OFF# 

STOP_PCI 

SUSA# 

STOP_CPU 

X 

CPUPERF# 

GPIO Function 

GPI 

GPI 

GPI 

GPI 

GPI 

GPI 

GPI 

GPI 

GPI 

GPI 

GPI 

GPI 

GPO 

GPO 

GPO 

GPO 

GPO 

GPO 

OD 

Power Plane 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

RESUME 

RESUME 

RESUME 

RESUME 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

Pin Name 

GPIO23 

GPIO24 

GPIO25 

GPIO27 

GPIO28 

GPIO32 

GPIO33 

GPIO34 

GPIO35 

GPIO36 

GPIO37 

GPIO38 

GPIO39 

GPIO40 

GPIO41 

GPIO42 

GPIO43 

MUX Function 

X 

PCLKRUN# 

X 

X 

X 

WIRELESS_PD# 

LCDID0 

LCDID1 

LCDID2 

SIDE_IN# 

ICH_SIDE_IN# 

IDERST# 

MINIPCI_ACT# 

DEBIG_EN 

SIDEDET 

SPK_OFF 

SIDERST# 

GPIO Function 

O 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

GPIO 

Power Plane 

MAIN 

RESUME 

RESUME 

RESUME 

RESUME 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

MAIN 

44


1.6 Appendix 2: MiTAC 8080 Product Specification 

CPU 

Chipset 

L2 Cache 

System BIOS 

Memory 

ROM Drive 

HDD 

Ext. FDD 

Display 

Video Controller 

Keyboard 

Button 

Pointing Device 

PCMCIA 

Card Reader 

- Intel Banias Processor CPU Support 1.4GHz ~ 1.7GHz or above 

- FSB 400MHz 

- Montara-GM + ICH4-M 

-1M 

- Flash EPROM (Include System BIOS and VGA BIOS) - ACPI 1.0b; DMI 2.3.1 compliant(P) 

- 0MB on board; Expandable to 1024MB 

- Expandable with combination of optional 128MB/256MB/512MB(P)memory 

- Two 200-pin DDR SDRAM Memory Module, PC 2100/1600 specifications 

- 24X CD ROM Drive 

- 8X DVD ROM Drive 

- 24X10x24 CD-RW or above 

- 16X10X8X24 Combo or above 

- 2X2X1X8X24X10X24 DVD Multi 

- 2.5’’9.5 mm height: 20/30/40/60GB; Support Ultra DMA 66/100 - Reseller Exchangeable 

- Support External FDD w/z USB I/F; 3.5" Format for 720KB/1.2MB/1.44MB 

- 14.1” XGA/SXGA+ TFT display; Resolution: 1024x768/1400x1050 

- Integrate in Northbridge - Support Multi Monitor - Ultra AGP 

- 19mm pitch/2.7mm stroke - Windows Logo Key x 1; Application Key x 1 

- 5x Easy Start Buttons (functions defined by user)I/ instant play for Audio CD When System off 

- 1xWireless RF ON/OFF 

- Glide pad with 6x buttons - Finger printer for option (P) 

- Type II x 1 - CardBus Support 

- 4 in 1 card reader for (MS,SM,SD,MMC) 

45

Continued to the previous table 

Audio System 

I/O Port 

Communication 

Power Supply 

AC Adapter 

Dimensions 

Weight 

Accessories 

Architecture 

Options 

318x275 mm, thickness 25~30mm 

2kg (P) 


- Sound Blaster Pro compatible - Built-in mono microphone - Support AC97 2.1 

- 2X Speakers (2 Watt each) 

- Standard USB2.0 port x 3 

- RJ-11 port x 1 

- RJ-45 port x 1 

- IR port x1, complies with IrDA 1.1 

- DC input x 1 

- VGA monitor port x1 

- Audio-out x 1 (S/PIDF) 

- Mic-in x 1 

- IEEE1394a Port x 1 

- S-Video Out Port (7 pins)x 1 (NTSC/PAL) 

- Built-in 56Kbps V.90 MDC modem 

- Built-in 10/100 based-T LAN 

- Built-in antenna for Mini-PCI wireless communication 

- 8-cell Li-ion (2200mAh/3.7V) Cylindrical Type 

- User swappable 

- Min Battery Life: 5 hrs (P) 

- Support Power on charge 

Universal AC adapter 60/70 W(P) ; Input: 100-240V, 50/60Hz AC 

Power Cord, AC Adapter, RJ-11 Phone Cable, Manual, System Driver CD-Title 

Support PC2001 Specification, Designed for Windows 2000 & Windows XP 

128MB/256MB/512MB DDR SDRAM, 8-cell Li-ION Battery Pack, AC Adapter w/o Power Cord, Notebook Carry Bag 

46

2. System View and Disassembly 

2.1 System View 

2.1.1 Front View 

1 

2 

3 

4 

5 

6 

Hold Switch 

Audio Play Button 

Card Reader Slot 

Audio Output 

Microphone Input 

Top Cover Latch 

2.1.2 Left-side View 

1 

2 

3 

4 

5 

6 

Power Jack 

VGA Port 

S-Video Output Connector 

USB Port 

RJ-45 Connector 

PC Card Slot 


 

 

 

47

2.1.3 Right-side View 

1 

2 

3 

4 

2.1.4 Rear View 

1 

2 

3 

4 

CD-ROM/DVD-ROM Drive 

USB Port 

1394 Port 

IR Module 

RJ-11 Connector 

Battery Charging LED Indicator 

Battery Power LED Indicator 

AC Power LED Indicator 


 

 

 

 

48

2.1.5 Bottom View 

1 

2 

3 

4 

Extend SO-DIMM Cover 

CPU Cover 

Hard Disk Drive Cover 

Battery Pack 

2.1.6 Top-open View 

1 

2 

3 

4 

5 

6 

7 

LCD Screen 

Stereo Speaker 

Battery Pack 

Power Button 

Keyboard 

Touch Pad 

Device Indicators 


 

 

 

 

 

 

 

 

 

 

 

49

2.2 System Disassembly 


The section discusses at length each major component for disassembly/reassembly and show corresponding 

illustrations. Use the chart below to determine the disassembly sequence for removing components from the 

notebook. 

NOTE: 1. Before you start to install/replace these modules, disconnect all peripheral devices and make sure 

the notebook is not turned on or connected to AC power. 

2. During disassembly, 1) Label each cable as you disconnect it, noting its position and routing; 

2) Keep all the screws. 

50

NOTEBOOK 


Modular Components 

LCD Assembly Components 

Base Unit Components 

2.2.1 Battery Pack 


2.2.3 CPU 

2.2.4 HDD Disk Drive 

2.2.5 CD/DVD-ROM Drive 

2.2.6 DDR SDRAM 

2.2.7 LCD Assembly 

2.2.8 Inverter Board 


2.2.10 System Board 

2.2.11 Modem Card 

2.2.12 Touch Pad 

51

2.2.1 Battery Pack 

Disassembly 


1. Carefully put the notebook upside down. 

2. Pull the battery pack out of the compartment () while sliding and holding the release levers outwards to the 

“unlock” ( ) position (). (Figure 2-1) 

Reassembly 

 

 

Figure 2-1 Remove the battery pack 

1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a 

clicking sound. 

2. Slide the release lever to the “lock” ( ) position. 

 

52


Disassembly 


1. Remove the battery pack. (See section 2.2.1 Disassembly) 

2. Open the top cover. Remove three screws fastening the keyboard. (Figure 2-2) 

Figure 2-2 Remove three screws Figure 2-3 Disconnect the cable 

4. Disconnect the cable from system board. (Figure 2-3) 

Reassembly 

1. Reconnect the keyboard cable 

2. Replace the keyboard and secure with three screws. 

2. Replace the battery pack. (See section 2.2.1 Reassembly) 

53

2.2.3 CPU 

Disassembly 

Figure 2-4 Remove five screws 




3. Remove five screws fastening the heatsink and DDR SDRAM’s compartment covers. (Figure 2-4) 

Figure 2-5 Remove the CPU compartment cover 

4. First, sliding out the DDR SDRAM compartment cover . And then you can easy to remove the CPU compartment 

cover. (Figure 2-5) 

54


5. Remove four spring screws fastening the heatsink. (Figure 2-6) 

Figure 2-6 Unscrew four screws 

Figure 2-7 Disconnect the fan’s cord 

6. Disconnect the fan’s power cord to detach the heatsink from the CPU compartment. (Figure 2-7) 

55


7. Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-8) 

Reassembly 

Figure 2-8 Remove the CPU 

1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into 

the holes. Tighten the screw by a flat screwdriver to locking the CPU. 

2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with four 

spring screws. 

3. First, replace the heatsink compartment cover. Then fit the DDR SDRAM compartment cover and secure them 

with five screws. 


56

2.2.4 HDD Module 

Disassembly 

Figure 2-9 Remove HDD module 




3. Remove two screws fastening the HDD compartment cover. Then sliding it outward. (Figure 2-9) 

Figure 2-10 Disassemble the hard disk 

4. To remove the hard disk drive, first unscrew one screw (), then sliding out the hard disk drive (). (Figure 2-10) 

 

 

57


5. Unscrew four screws to remove the hard disk drive from the holding. (Figure 2-11) 

Reassembly 

Figure 2-11 Free the hard disk 

1. Fit the hard disk drive into the holding and secure with four screws. 

2. Replace the hard disk drive into compartment and secure with one screws. 

3. Replace the HDD’s cover and secure with two screws. 

4. Replace the keyboard. (See section 2.2.2 Reassembly) 

5. Then replace battery pack. (See section 2.2.1 Reassembly) 

58

2.2.5 CD/DVD-ROM Drive 

Disassembly 




3. Pull the CD/DVD-ROM out of the compartment () while sliding and holding the release lever outwards to the 

“unlock” ( ) position (). (Figure 2-12) 

Reassembly 

 

 

Figure 2-12 Remove CD/DVD-ROM 

1. Push the battery pack into the compartment. The battery pack should be correctly connected when you hear a 

clicking sound. 

2. Ensure the release lever being the “lock” ( ) position. 


59

2.2.6 DDR SDRAM 

Disassembly 




3. Remove one screw to access the DDR-SARAM’s socket. (Figure 2-13) 

4. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-14) 

Reassembly 

Figure 2-13 Remove the compartment cover Figure 2-14 Remove the DDR SDRAM 

1. To install the DDR-SDRAM, match the its notched part with the socket's projected part and firmly insert the SDRAM 

into the socket at 20-degree angle. Then push down until the retaining clips lock the SO-DIMM into position. 

2. Replace the DDR-SDRAM compartment cover and secure with one screw. 


60

2.2.7 LCD Assembly 

Disassembly 




3. Remove nine screws. (Figure 2-15) 

4. Remove the heatsink. (See the steps 3, 4, 5 of section 2.2.3 Disassembly) 

5. Disconnect two wires from system board in heatsink compartment. (Figure 2-16) 

Figure 2-15 Unscrew nine screws Figure 2-16 Disconnect two wires 

61


6. Carefully turnover the notebook. Close the top cover, remove three hinge covers. Then lift up the LCD ASSY. 

(Figure 2-17) 

Reassembly 

Figure 2-17 Remove the hinge covers 

1. Replace the LCD Assembly and reconnect two wires. 

2. Replace the heatsink, heatsink compartment cover and DDR SDRAM compartment cover. (See the step 2, 3 of 

section 2.2.3 Reassembly) 

3. Fasten the LCD Assembly by four screws. 

4. Fit three hinge covers. 


62

2.2.8 Inverter Board 

Disassembly 




3. Remove the LCD Assembly. (See section 2.2.7 Disassembly) 

4. Remove the five rubber pads and five screws. (figure 2-18) 

5. Insert a flat screwdriver to the lower part of the top cover and gently pry the frame out. Repeat the process until the 

cover is completely separated from the housing. 

6. Disconnect one wire from inverter board and remove two screws fastening the inverter board. (Figure 2-19) 

Figure 2-18 Unscrew five screws Figure 2-19 Disconnect one cables 

63

Reassembly 


1. Fit the inverter board back into place and secure with two screws, and reconnect the wire to the inverter board. . 

2. Fit the LCD top cover back into the housing and secure with five screws and five rubber pads 

3. Replace the LCD Assembly. (See section 2.2.7 Reassembly) 


64


Disassembly 




3. Remove the LCD Assembly. (See section 2.2.7 Disassembly) 

4. Remove the inverter board. (See section 2.2.8 Disassembly) 

5. Remove four screws. And then lift up LCD panel. (Figure 2-20) 

6. To free the LCD panel, remove six screws. (Figure 2-21) 

Figure 2-20 Unscrew four screws Figure 2-21 Unscrew six screws 

65

Reassembly 


1. Attach the LCD panel holding to panel and secure with six screws. 

2. Fit the LCD panel into place and secure with four screws. 

3. Replace the inverter board. (See section 2.2.8 Reassembly) 

4. Replace the LCD assembly. (See section 2.2.7 Reassembly) 


66

2.2.10 System Board 

Disassembly 




3. Remove the keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR-SDRAM and LCD Assembly. (See the 

previous sections Disassembly) 

4. Remove nine screws on the bottom of notebook. (Figure 2-22) 

5. Disconnect the speaker’s cord from system board in the heatsink compartment. (Figure 2-23) 

Figure 2-22 Unscrew nine screws Figure 2-23 Disconnect the cord 

67


6. Carefully, turnover the notebook. Then remove seven screws. (Figure 2-24) 

Figure 2-24 Unscrew seven screws Figure 2-25 Disconnect the cord 

7. Lift notebook up carefully. Disconnect the speaker’s cord. (Figure 2-25) 

68


8. Disconnect the touch pad’s cable. Then lift up the system top cover. (Figure 2-26) 

Figure 2-26 Disconnect the cable 

Figure 2-27 Unscrew screws and hex nuts 

9. Remove five screws and two hex nuts beside the VGA port. Now you can lift up system board from housing. 

(Figure 2-27) 

69

Reassembly 


1. Fit the system board back into housing and secure with five screws and two hex nuts. 

2. Reconnect the touch pad’s cable to system board. 

3. Reconnect the speaker’s cord to system board. 

4. Then fit the system top cover and secure with seven screws. 

5. Up the notebook upside down. Reconnect the other speaker’s cord. 

6. Fasten the housing by nine screws. 

7. Reassemble the notebook. (See the previous sections Reassembly) 

70

2.2.11 Modem Card 

Disassembly 

Reassembly 






4. Remove the system top cover. (See the steps 3 to 7 of section 2.2.10 Disassembly) 

5. Remove two screws fastening the modem card. disconnect cord from system board. (Figure 2-28) 

Figure 2-28 Remove the modem card 

1. Reconnect the cord. Then fit the modem card and secure with two screws. 


71

2.2.12 Touch Pad 

Disassembly 






4. Remove the system top cover. (See the steps 3 to 7 of section 2.2.10 Disassembly) 

5. Remove four screws fastening the touch pad bracket. Then remove it. (Figure 2-29) 

6. Remove the click holder and touch pad panel. (Figure 2-30) 

Figure 2-29 Disconnect the cable 

Figure 2-30 Unscrew screws and hex nuts 

72

Reassembly 


1. Fit the touch pad panel and click holder 

2. Then fit the touch pad bracket and secure with four screws. 


73

3.1 Main Board (Side A) – 1 


3. Definition & Location of Connectors / Switches 

SW501 

J518 

J519 

J509 

J516 

J517 

J515 

J514 

J513 

J512 

J510 

J509 

J511 

J508 

J520 

J507 

J506 

J505 

J501 

J504 

PJ501 

J503 

J502 

PJ501 : AC Power Jack 

J501 : Battery Connector 

J502 : Fan Connector 

J503 : Left Internal Speaker Jack 

J504 : Inverter Board Connector 

J505 : LCD Connector 

J506 : DC to DC Board Connector 

J507 : External VGA Connector 

J508 : S-Video Connector 

J509 : Secondary EIDE Connector 

J510 : USB Port Connector 

------ To next page ------ 

74

3.1 Main Board (Side A) – 2 



SW501 

J518 

J519 

J509 

J516 

J517 

J515 

J514 

J513 

J512 

J510 

J509 

J511 

J508 

J520 

J507 

J506 

J505 

J501 

J504 

PJ501 

J503 

J502 

------ Continued to previous page ------ 

J511 : RTC Battery Connector 


J513, J514 : DDR SO-DIMM Module Socket 

J515 : RJ-45 Connector 

J516 : Card Reader Socket 

J517 : PCMCIA Card Socket 

J518 : Line Out Jack 

J519 : External Microphone Jack 

J520 : Mini PCI Socket 

SW501 : Audio DJ Button 

75


3. Definition & Location of Connectors/ Switches 

3.1 Main Board (Side B) 

J1 

SW2 

J2 

J509 

J3 

J4 

SW5 

SW7 

SW3 SW8 

SW6 

SW4 

J1 : Internal Keyboard Connector 

J2 : Touch-Pad Connector 

J3 : MDC Jump Wire Connector 

J4 : Primary EIDE Connector 

SW2 : LCD ID Select Switch 

SW3, SW8 : SCRL Up / Down Switch 

SW6, SW7 : SCRL Left / Right Switch 

SW4, SW5 : Left / Right Switch 

76



3.2 DC to DC Board 

J1 J2 

J4 

J6 

J7 

SW1 

J3 

U2 

J5 

J1 : DC to DC Board Connector 

J2 : Modem Daughter Board (MDC) Connector 


J4 : Right Internal Speaker Connector 

J5 : IEEE1394 Port Connector 

J6 : MDC Jump Wire Connector 

J7 : RJ-11 Connector 

U2 : FIR Module 

SW2 : Power Button 

77


4. Definition & Location of Major Components 

4.1 Main Board (Side A) 

J509 

U511 

U509 

U510 

U504 

U502 

PU502 

PU505 

U501 

U501 : Intel Banais Micro-FCPGA Processor 

U502 : Intel 82855GM GMCH 

U504 : H8/F3437 Micro Controller 

U509 : STAC9570 Audio Codec 

U510 : PC87393 Super I/O Controller 

U511 : APA2020A Audio Amplifier 

PU502 : LTC3728L +1.05V / +1.2V Voltage Converter 

PU505 : MAX1907 CPU Core Voltage Converter 

78


4. Definition & Location of Major Components 

4.1 Main Board (Side B) 

PU2 

U3 U9 

U4 

U7 

PU22 

U11 

PU23 

J509 

U15 

U17 

U21 

U19 

U3 : Intel 82801DBM ICH4-M 

U4 : PLL207-151 Clock Generator 

U7 : CH7011A TV Encode 

U9 : VT6307 IEEE1394 Controller 

U11 : LF-H80P LAN Buffer 

U15 : VT6105-LOM LAN Controller 

U17 : CB710 CardBus & Card Reader Controller 

U19 : System Flash BIOS 

U21 : TPS2211A Power Switch 

PU2 : TL594C Battery Charging 

PU22 : +1.25V_DDR/+2.5V_DDR Voltage Converter 

PU23 : LTC3728L +3V/+5V Voltage Converter 

79


5. Pin Descriptions of Major Components 

5.1 Intel Pentium M Processor 

Signal Name Type Description 

A[31:3]# 

I/O A[31:3]# (Address) define a 2 32 -byte physical memory address space. 

In sub-phase 1 of the address phase, these pins transmit the address of a 

transaction. In sub-phase 2, these pins transmit transaction type 

information. These signals must connect the appropriate pins of both 

agents on the Intel Pentium M processor system bus. A[31:3]# are source 

synchronous signals and are latched into the receiving buffers by 

ADSTB[1:0]#. Address signals are used as straps which are sampled 

before RESET# is deasserted. 

A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical 

address bit 20 (A20#) before looking up a line in any internal cache and 

before driving a read/write transaction on the bus. Asserting A20M# 

emulates the 8086 processor's address wrap-around at the 1-Mbyte 

boundary. Assertion of A20M# is only supported in real mode. 

A20M# is an asynchronous signal. However, to ensure recognition of 

this signal following an Input/Output write instruction, it must be valid 

along with the TRDY# assertion of the corresponding Input/Output 

Write bus transaction. 

ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the 

transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents 

observe the ADS# activation to begin parity checking, protocol 

checking, address decode, internal snoop, or deferred reply ID match 

operations associated with the new transaction. 

ADSTB[1:0]# I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising 

and falling edges. Strobes are associated with signals as shown below. 

Signals Associated Strobe 

REQ[4:0]#, A[16:3]# ADSTB[0]# 

A[31:17]# ADSTB[1]# 

BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the system bus 

frequency. All processor system bus agents must receive these signals to 

drive their outputs and latch their inputs. 

BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent 

that is unable to accept new bus transactions. During a bus stall, the 

BPM[2:0]# 

BPM[3] 

O 

I/O 

current bus owner cannot issue any new transactions. 

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance 

monitor signals. They are outputs from the processor that indicate the 

status of breakpoints and programmable counters used for monitoring 

processor performance. BPM[3:0]# should connect the appropriate pins 

of all Intel Pentium M processor system bus agents. This includes debug 

or performance monitoring tools. 


BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the 

processor system bus. It must connect the appropriate pins of both 

processor system bus agents. Observing BPRI# active (as asserted by 

the priority agent) causes the other agent to stop issuing new requests, 

unless such requests are part of an ongoing locked operation. The 

priority agent keeps BPRI# asserted until all of its requests are 

completed, then releases the bus by deasserting BPRI#. 

BR0# I/O BR0# is used by the processor to request the bus. The arbitration is done 

between the Intel Pentium M processor (Symmetric Agent) and the 

MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM 

chipset. 

COMPP3:0] Analog COMP[3:0] must be terminated on the system board using precision 

(1% tolerance) resistors. Refer to the platform design guides for more 

implementation details. 

D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data 

path between the processor system bus agents, and must connect the 

appropriate pins on both agents. The data driver asserts DRDY# to 

indicate a valid data transfer. 

D[63:0]# are quad-pumped signals and will thus be driven four times in 

a common clock period. D[63:0]# are latched off the falling edge of 

both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals 

correspond to a pair of one DSTBP# and one DSTBN#. The following 

table shows the grouping of data signals to data strobes and DINV#. 

Quad-Pumped Signal Groups 

Data Group DSTBN#/DSTBP# DINV# 

D[15:0]# 0 0 

D[31:16]# 1 1 

D[47:32]# 2 2 

D[63:48]# 3 3 

DBR# O 

Furthermore, the DINV# pins determine the polarity of the data signals. 

Each group of 16 data signals corresponds to one DINV# signal. When 

the DINV# signal is active, the corresponding data group is inverted and 

therefore sampled active high. 

DBR# (Data Bus Reset) is used only in processor systems where no 

debug port is implemented on the system board. DBR# is used by a 

debug port interposer so that an in-target probe can drive system reset. If 

a debug port is implemented in the system, DBR# is a no connect. 

DBR# is not a processor signal. 

80



DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving 

data on the processor system bus to indicate that the data bus is in use. 

The data bus is released after DBSY# is deasserted. This signal must 

connect the appropriate pins on both processor system bus agents. 

DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be 

guaranteed in-order completion. Assertion of DEFER# is normally the 

responsibility of the addressed memory or Input/Output agent. This 

signal must connect the appropriate pins of both processor system bus 

agents. 

DINV[3:0]# I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate 

the polarity of the D[63:0]# signals. The DINV[3:0]# signals are 

activated when the data on the data bus is inverted. The bus agent will 

invert the data bus signals if more than half the bits, within the covered 

group, would change level in the next cycle. 

DINV[3:0]# Assignment To Data Bus 

Bus Signal Data Bus Signals 

DINV[3]# D[63:48]# 

DINV[2]# D[47:32]# 

DINV[1]# D[31:16]# 

DINV[0]# D[15:0]# 

DPSLP# I DPSLP# when asserted on the platform causes the processor to 

transition from the Sleep state to the Deep Sleep state. In order to return 

to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the 

ICH4-M component and also connects to the MCH-M component of the 

Intel 855PM or Intel 855GM chipset. 

DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data 

transfer, indicating valid data on the data bus. In a multi-common clock 

data transfer, DRDY# may be deasserted to insert idle clocks. This 

signal must connect the appropriate pins of both processor system bus 

agents. 

DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#. 


D[15:0]#, DINV[0]# DSTBN[0]# 

D[31:16]#, DINV[1]# DSTBN[1]# 

D[47:32]#, DINV[2]# DSTBN[2]# 

D[63:48]#, DINV[3]# DSTBN[3]# 

DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. 


D[15:0]#, DINV[0]# DSTBP[0]# 

D[31:16]#, DINV[1]# DSTBP[1]# 

D[47:32]#, DINV[2]# DSTBP[2]# 

D[63:48]#, DINV[3]# DSTBP[3]# 



DPWR# I DPWR# is a control signal from the Intel 855PM and Intel 855GM 

chipsets used to reduce power on the Intel Pentium M data bus input 

buffers. 

FERR#/PBE# O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a 

multiplexed signal and its meaning is qualified by STPCLK#. When 

STPCLK# is not asserted, FERR#/PBE# indicates a floating point when 

the processor detects an unmasked floating-point error. FERR# is 

similar to the ERROR# signal on the Intel 80387 coprocessor, and is 

included for compatibility with systems using MS-DOS* type 

floating-point error reporting. When STPCLK# is asserted, an assertion 

of FERR#/PBE# indicates that the processor has a pending break event 

waiting for service. The assertion of FERR#/PBE# indicates that the 

processor should be returned to the Normal state. When FERR#/PBE# is 

asserted, indicating a break event, it will remain asserted until 

STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active 

will also cause an FERR# break event. 

GTLREF I GTLREF determines the signal reference level for AGTL+ input pins. 

GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+ 

HIT# 

HITM# 

I/O 

I/O 

receivers to determine if a signal is a logical 0 or logical 1. 

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop 

operation results. Either system bus agent may assert both HIT# and 

HITM# together to indicate that it requires a snoop stall, which can be 

continued by reasserting HIT# and HITM# together. 

IERR# O IERR# (Internal Error) is asserted by a processor as the result of an 

internal error. Assertion of IERR# is usually accompanied by a 

SHUTDOWN transaction on the processor system bus. This transaction 

may optionally be converted to an external error signal (e.g., NMI) by 

system core logic. The processor will keep IERR# asserted until the 

assertion of RESET#, BINIT#, or INIT#. 

IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to 

ignore a numeric error and continue to execute noncontrol floating-point 

instructions. If IGNNE# is deasserted, the processor generates an 

exception on a noncontrol floating-point instruction if a previous 

floating-point instruction caused an error. IGNNE# has no effect when 

the NE bit in control register 0 (CR0) is set. 

IGNNE# is an asynchronous signal. However, to ensure recognition of 

this signal following an Input/Output write instruction, it must be valid 

along with the TRDY# assertion of the corresponding Input/Output 

Write bus transaction. 

REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of 

both processor system bus agents. They are asserted by the current bus 

owner to define the currently active transaction type. These signals are 

source synchronous to ADSTB[0]#. 

81



INIT# 

I INIT# (Initialization), when asserted, resets integer registers inside the 

processor without affecting its internal caches or floating-point registers. 

The processor then begins execution at the power on Reset vector 

configured during power on configuration. The processor continues to 

handle snoop requests during INIT# assertion. INIT# is an asynchronous 

signal. However, to ensure recognition of this signal following an 

Input/Output Write instruction, it must be valid along with the TRDY# 

assertion of the corresponding Input/Output Write bus transaction. 

INIT# must connect the appropriate pins of both processor system bus 

agents. If INIT# is sampled active on the active to inactive transition of 

RESET#, then the processor executes its Built-in Self-Test (BIST) 

LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of 

all APIC Bus agents. When the APIC is disabled, the LINT0 signal 

becomes INTR, a maskable interrupt request signal, and LINT1 

becomes NMI, a nonmaskable interrupt. INTR and NMI are backward 

compatible with the signals of those names on the Pentium processor. 

Both signals are asynchronous. 

Both of these signals must be software configured using BIOS 

programming of the APIC register space and used either as NMI/INTR 

or LINT[1:0]. Because the APIC is enabled by default after Reset, 

operation of these pins as LINT[1:0] is the default configuration. 

LOCK# I/O LOCK# indicates to the system that a transaction must occur atomically. 

This signal must connect the appropriate pins of both processor system 

bus agents. For a locked sequence of transactions, LOCK# is asserted 

from the beginning of the first transaction to the end of the last 

transaction. 

When the priority agent asserts BPRI# to arbitrate for ownership of the 

processor system bus, it will wait until it observes LOCK# deasserted. 

This enables symmetric agents to retain ownership of the processor 

system bus throughout the bus locked operation and ensure the 

atomicity of lock. 

PRDY# 

O Probe Ready signal used by debug tools to determine processor debug 

readiness. 

PREQ# I Probe Request signal used by debug tools to request debug operation of 

the processor. 

PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor 

temperature monitoring sensor detects that the processor has reached its 

maximum safe operating temperature. This indicates that the processor 

Thermal Control Circuit has been activated, if enabled. 

This signal may require voltage translation on the motherboard. 

PSI# O Processor Power Status Indicator signal. This signal is asserted when the 

processor is in a lower state (Deep Sleep and Deeper Sleep). 



PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor requires 

this signal as a clean indication that the clocks and power supplies are 

stable and within their specifications. ‘Clean’ implies that the signal will 

remain low (capable of sinking leakage current), without glitches, from 

the time that the power supplies are turned on until they come within 

specification. The signal must then transition monotonically to a high 

state. PWRGOOD can be driven inactive at any time, but clocks and 

power must again be stable before a subsequent rising edge of 

PWRGOOD. 

The PWRGOOD signal must be supplied to the processor; it is used to 

protect internal circuits against voltage sequencing issues. It should be 

driven high throughout the boundary scan operation. 

ITP_CLK[1:0] I ITP_CLK[1:0] are copies of BCLK that are used only in processor 

systems where no debug port is implemented on the system board. 

ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port 

implemented on an interposer. If a debug port is implemented in the 

system, ITP_CLK[1:0] are no connects. These are not processor signals. 

RESET# I Asserting the RESET# signal resets the processor to a known state and 

invalidates its internal caches without writing back any of their contents. 

For a power-on Reset, RESET# must stay active for at least two 

milliseconds after VCC and BCLK have reached their proper 

specifications. On observing active RESET#, both system bus agents 

will deassert their outputs within two clocks. All processor straps must 

be valid within the specified setup time before RESET# is deasserted. 

RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent 

responsible for completion of the current transaction), and must connect 

the appropriate pins of both processor system bus agents. 

RSVD - These pins are RESERVED and must be left unconnected on the board. 

However, it is recommended that routing channels to these pins on the 

board be kept open for possible future use. Please refer to the platform 

design guides for more details. 

SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to 

enter the Sleep state. During Sleep state, the processor stops providing 

internal clock signals to all units, leaving only the Phase-Locked Loop 

(PLL) still operating. Processors in this state will not recognize snoops 

or interrupts. The processor will recognize only assertion of the 

RESET# signal, deassertion of SLP#, and removal of the BCLK input 

while in Sleep state. If SLP# is deasserted, the processor exits Sleep 

state and returns to Stop-Grant state, restarting its internal clock signals 

to the bus and processor core units. If DPSLP# is asserted while in the 

Sleep state, the processor will exit the Sleep state and transition to the 

Deep Sleep state. 

82


SMI# I SMI# (System Management Interrupt) is asserted asynchronously by 

system logic. On accepting a System Management Interrupt, the 

processor saves the current state and enter System Management Mode 

(SMM). An SMI Acknowledge transaction is issued, and the processor 

begins program execution from the SMM handler. 

If SMI# is asserted during the deassertion of RESET# the processor will 

tristate its outputs. 

STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter a 

low power Stop-Grant state. The processor issues a Stop-Grant 

Acknowledge transaction, and stops providing internal clock signals to 

all processor core units except the system bus and APIC units. The 

processor continues to snoop bus transactions and service interrupts 

while in Stop-Grant state. When STPCLK# is deasserted, the processor 

restarts its internal clock to all units and resumes execution. The 

assertion of STPCLK# has no effect on the bus clock; STPCLK# is an 

asynchronous input. 

TCK I TCK (Test Clock) provides the clock input for the processor Test Bus 

(also known as the Test Access Port). 

TDI I TDI (Test Data In) transfers serial test data into the processor. TDI 

provides the serial input needed for JTAG specification support. 

TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO 

TEST1, 

TEST2, 

TEST3 


provides the serial output needed for JTAG specification support. 

I TEST1, TEST2, and TEST3 must be left unconnected but should have a 

stuffing option connection to V SS separately using 1-k, pull-down 

resisitors. 

THERMDA Other Thermal Diode Anode. 

THERMDC Other Thermal Diode Cathode. 

THERMTRIP# O The processor protects itself from catastrophic overheating by use of an 

internal thermal sensor. This sensor is set well above the normal 

operating temperature to ensure that there are no false trips. The 

processor will stop all execution when the junction temperature exceeds 

approximately 125°C. This is signalled to the system by the 

THERMTRIP# (Thermal Trip) pin. 

TMS I TMS (Test Mode Select) is a JTAG specification support signal used by 

debug tools. 

TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is 

ready to receive a write or implicit writeback data transfer. TRDY# 

must connect the appropriate pins of both system bus agents. 

TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# 

must be driven low during power on Reset. 



VCC I Processor core power supply. 

VCCA[3:0] I VCCA provides isolated power for the internal processor core PLL’s. 

VCCP I Processor I/O Power Supply. 

VCCQ[1:0] I Quiet power supply for on die COMP circuitry. These pins should be 

connected to VCCP on the motherboard. However, these connections 

should enable addition of decoupling on the VCCQ lines if necessary. 

VCCSENSE O VCCSENSE is an isolated low impedance connection to processor core 

power (VCC ). It can be used to sense or measure power near the silicon 

with little noise. 

VID[5:0] O VID[5:0] (Voltage ID) pins are used to support automatic selection of 

power supply voltages (Vcc). Unlike some previous generations of 

processors, these are CMOS signals that are driven by the Intel Pentium 

M processor. The voltage supply for these pins must be valid before the 

VR can supply Vcc to the processor. Conversely, the VR output must be 

disabled until the voltage supply for the VID pins becomes valid. The 

VID pins are needed to support the processor voltage specification 

variations. 

VSSSENSE O VSSSENSE is an isolated low impedance connection to processor core 

VSS. It can be used to sense or measure ground near the silicon with 

little noise. 

83


5.2 Intel 82855GM Graphics and Memory Controller Hub (GMCH) 

Host Interface Signals 


ADS# I/O 

AGTL+ 

BNR# I/O 

AGTL+ 

BPRI# O 

AGTL+ 

BREQ0# I/O 

AGTL+ 

CPURST# O 

AGTL+ 

DBSY# I/O 

AGTL+ 

DEFER# O 

AGTL+ 

DPSLP# I 

CMOS 

HD[63:0]# I/O 

AGTL+ 

Address Strobe: The system bus owner asserts ADS# to indicate 

the first of two cycles of a request phase. The GMCH can assert this 

signal for snoop cycles and interrupt messages. 

Block Next Request: Used to block the current request bus owner 

from issuing a new request. This signal is used to dynamically 

control the CPU bus pipeline depth. 

Bus Priority Request: The GMCH is the only Priority Agent on the 

system bus. It asserts this signal to obtain the ownership of the 

address bus. This signal has priority over symmetric bus requests 

and will cause the current symmetric owner to stop issuing new 

transactions unless the HLOCK# signal was asserted. 

Bus Request 0#: The GMCH pulls the processor bus BREQ0# 

signal low during 

CPURST#. The signal is sampled by the processor on the 

active-to-inactive transition of CPURST#. The minimum setup time 

for this signal is 4 BCLKs. The minimum hold time is 2 clocks and 

the maximum hold time is 20 BCLKs. BREQ0# should be tristated 

after the hold time requirement has been satisfied. 

During regular operation, the GMCH will use BREQ0# as an early 

indication for PSB Address and Ctl input buffer and sense amp 

activation. 

CPU Reset: The CPURST# pin is an output from the GMCH. The 

GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) 

is asserted and for approximately 1 ms after RESET# is deasserted. 

The CPURST# allows the processor to begin execution in a known 

state. 

Note that the ICH4-M must provide CPU strap set-up and 

hold-times around CPURST#. This requires strict synchronization 

between GMCH, CPURST# deassertion and ICH4-M driving the 

straps. 

Data Bus Busy: Used by the data bus owner to hold the data bus for 

transfers requiring more than one cycle. 

Defer: GMCH will generate a deferred response as defined by the 

rules of the GMCH’s Dynamic Defer policy. The GMCH will also 

use the DEFER# signal to indicate a CPU retry response. 

Deep Sleep #: This signal comes from the ICH4-M device, 

providing an indication of C3 and C4 state control to the CPU. 

Deassertion of this signal is used as an early indication for C3 and 

C4 wake up (to active HPLL). Note that this is a low-voltage 

CMOS buffer operating on the PSB VTT power plane. 

Host Data: These signals are connected to the CPU data bus. 

HD[63:0]# are transferred at 4x rate. Note that the data signals are 

inverted on the CPU bus. 


DINV[3:0]# I/O 

AGTL+ 

HA[31:0]# I/O 

AGTL+ 

HADSB[1:0]# I/O 

AGTL+ 

DRDY# I/O 

AGTL+ 

HDSTBP[3:0]# I/O 

HDSTBN[3:0]# AGTL+ 

HIT# I/O 

AGTL+ 

HITM# I/O 

AGTL+ 

HLOCK# I/O 

AGTL+ 

Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. 

Indicates if the associated signals are inverted or not. DINV[3:0]# 

are asserted such that the number of data bits driven electrically low 

(low voltage) within the corresponding 16-bit group never exceeds 

8. 

DINV# Data Bits 

DNIV[3]# HD[63:48]# 

DNIV[2]# HD[47:32]# 

DINV[1]# HD[31:16]# 

DINV[0]# HD[15:0]# 

Host Address Bus: HA[31:3]# connects to the CPU address bus. 

During processor cycles the HA[31:3]# are inputs. The GMCH 

drives HA[31:3]# during snoop cycles on behalf of Hub Interface. 

HA[31:3]# are transferred at 2x rate. Note that the address is 

inverted on the CPU bus. 

Host Address Strobe: HA[31:3]# connects to the CPU address bus. 

During CPU cycles, the source synchronous strobes are used to 

transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate. 

Strobe Address Bits 

HADSTB[0]# HA[16:3]#, HREQ[4:0]# 

HADSTB[1]# HA[31:17]# 

Data Ready: Asserted for each cycle that data is transferred. 

Differential Host Data Strobes: The differential source 

synchronous strobes are used to transfer HD[63:0]# and 

DINV[3:0]# at the 4x transfer rate. 

Strobe Data Bits 

HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]# 




Hit: Indicates that a caching agent holds an unmodified version of 

the requested line. Also, driven in conjunction with HITM# by the 

target to extend the snoop window. 

Hit Modified: Indicates that a caching agent holds a modified 

version of the requested line and that this agent assumes 

responsibility for providing the line. 

Also, driven in conjunction with HIT# to extend the snoop window. 

Host Lock: All CPU bus cycles sampled with the assertion of 

HLOCK# and ADS#, until the negation of HLOCK# must be 

atomic, i.e. no Hub Interface snoopable access to System Memory is 

allowed when HLOCK# is asserted by the CPU. 

84



Host Interface Signals (Continued) 


HREQ[4:0]# I/O 

AGTL+ 

HTRDY# O 

AGTL+ 

RS[2:0]# O 

AGTL+ 

Host Request Command: Defines the attributes of the request. 

HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting 

agent during both halves of the Request Phase. In the first half the 

signals define the transaction type to a level of detail that is 

sufficient to begin a snoop request. In the second half the signals 

carry additional information to define the complete transaction type. 

Host Target Ready: Indicates that the target of the processor 

transaction is able to enter the data transfer phase. 

Response Status: Indicates type of response according to the 

following the table: 

RS[2:0] Response type 

000 Idle state 

001 Retry response 

010 Deferred response 

011 Reserved (not driven by MCH-M) 

100 Hard Failure (not driven by MCH-M) 

101 No data response 

110 Implicit Write back 

111 Normal data response 

DDR SDRAM Interface Signals 


SCS [3:0]# O 

SSTL_2 

SMA[12:0] O 

SSTL_2 

SBA[1:0] O 

SSTL_2 

SRAS# O 

SSTL_2 

SCAS# O 

SSTL_2 

Chip Select: These pins select the particular DDR SDRAM 

components during the active state. 

Note: There is one SCS# per DDR-SDRAM Physical SO-DIMM 

device row. These signals can be toggled on every rising System 

Memory Clock edge. 

Multiplexed Memory Address: These signals are used to provide 

the multiplexed row and column address to DDR SDRAM. 

Bank Select (Memory Bank Address): These signals define which 

banks are selected within each DDR SDRAM row. The SMA and 

SBA signals combine to address every possible location within a 

DDR SDRAM device. 

DDR Row Address Strobe: SRAS# may be heavily loaded and 

requires tw0 DDR SDRAM clock cycles for setup time to the DDR 

SDRAMs. Used with SCAS# and SWE# (along with SCS#) to 

define the System Memory commands. 

DDR Column Address Strobe: SCAS# may be heavily loaded and 

requires two clock cycles for setup time to the DDR SDRAMs. 

Used with SRAS# and SWE# (along with SCS#) to define the 

System Memory commands. 


SWE# O 

SSTL_2 

SDQ[71:0] I/O 

SSTL_2 

SDQS[8:0] I/O 

SSTL_2 

SCKE[3:0] O 

SSTL_2 

SMAB[5,4,2,1] O 

SSTL_2 

SDM[8:0] O 

SSTL_2 

RCVENOUT# O 

SSTL_2 

RCVENIN# I 

SSTL_2 

Write Enable: Used with SCAS# and SRAS# (along with SCS#) to 

define the DDR SDRAM commands. SWE# is asserted during 

writes to DDR SDRAM. SWE# may be heavily loaded and requires 

two clock cycles for setup time to the DDR SDRAMs. 

Data Lines: These signals are used to interface to the DDR 

SDRAM data bus. 

NOTE: ECC error detection is supported: by the SDQ[71:64] 

signals. 

Data Strobes: Data strobes are used for capturing data. During 

writes, SDQS is centered on data. During reads, SDQS is edge 

aligned with data. The following list matches the data strobe with 

the data bytes. 

There is an associated data strobe (DQS) for each data signal (DQ) 

and check bit (CB) group. 

SDQS[7] -> SDQ[63:56] 

SDQS[6] -> SDQ[55:48] 

SDQS[5] -> SDQ[47:40] 

SDQS[4] -> SDQ[39:32] 

SDQS[3] -> SDQ[31:24] 

SDQS[2] -> SDQ[23:16] 

SDQS[1] -> SDQ[15:8] 

SDQS[0] -> SDQ[7:0] 

NOTE: ECC error detection is supported by the SDQS[8] signal. 

Clock Enable: These pins are used to signal a self-refresh or power 

down command to the DDR SDRAM array when entering system 

suspend. SCKE is also used to dynamically power down inactive 

DDR SDRAM rows. There is one SCKE per DDR SDRAM row. 

These signals can be toggled on every rising SCK edge. 

Memory Address Copies: These signals are identical to 

SMA[5,4,2,1] and are used to reduce loading for selective 

CPC(clock-per-command). These copies are not inverted. 

Data Mask: When activated during writes, the corresponding data 

groups in the DDR SDRAM are masked. There is one SDM for 

every eight data lines. SDM can be sampled on both edges of the 

data strobes. 

NOTE: ECC error detection is supported by the SDM[8] signal. 

Clock Output: Reserved, NC. 

Clock Input: Reserved, NC. 

85



Hub Interface Signals 


HI_[10:0] I/O 

Hub 

HI_STB I/O 

Hub 

HI_STB# I/O 

Hub 

Packet Data: Data signals used for HI read and write operations. 

Packet Strobe: One of two differential strobe signals used to 

transmit or receive packet data over HI. 

Packet Strobe Complement: One of two differential strobe signals 

used to transmit or receive packet data over HI. 

Clock Signals 


Host Processor Clocking 

BC.LK 

BCLK# 

I 

CMOS 

System Memory Clocking 

SCK[5:0] O 

SSTL_2 

SCK[5:0]# O 

SSTL_2 

DVO/Hub Input Clocking 

GCLKIN I 

CMOS 

DVO Clocking 

DVOBC.LK 

O 

DVOBCLK# DVO 

Differential Host Clock In: These pins receive a buffered host 

clock from the external clock synthesizer. This clock is used by all 

of the GMCH logic that are in the Host clock domain (Host, Hub 

and System Memory). The clock is also the reference clock for the 

graphics core PLL. This is a low voltage differential input. 

Differential DDR SDRAM Clock: SCK and SCK# pairs are 

differential clock outputs. The crossing of the positive edge of SCK 

and the negative edge of SCK# is used to sample the address and 

control signals on the DDR SDRAM. There are 3 pairs to each 

SO-DIMM. 

NOTE: ECC error detection is supported by the SCK[2] and 

SCK[5] signals. 

Complementary Differential DDR SDRAM Clock: These are the 

complimentary differential DDR SDRAM clock signals. 

NOTE: ECC error detection is supported by the SCK[2]# and 

SCK[5]# signals. 

Input Clock: 66-MHz, 3.3-V input clock from external buffer 

DVO/Hub Interface. 

Differential DVO Clock Output: These pins provide a differential 

pair reference clock that can run up to 165-MHz. 

DVOBCLK corresponds to the primary clock out. 

DVOBCLK# corresponds to the primary complementary clock out. 

DVOBCLK and DVOBCLK# should be left as NC (“Not 

Connected”) if the DVO B port is not implemented. 


DVOCC.LK 

DVOCCLK# 

O 

DVO 

DVOBCCLKINT I 

DVO 

DPMS I 

DVO 

DAC Clocking 

Differential DVO Clock Output: These pins provide a differential 

pair reference clock that can run up to 165-MHz. 

DVOCCLK corresponds to the primary clock out. 

DVOCCLK# corresponds to the primary complementary clock out. 

DVOCCLK and DVOCCLK# should be left as NC (“Not 

Connected”) if the DVO C port is not implemented. 

DVOBC Pixel Clock Input/Interrupt: This signal may be selected 

as the reference input to either dot clock PLL (DPLL) or may be 

configured as an interrupt input. A TV-out device can provide the 

clock reference. The maximum input frequency for this signal is 85 

-MHz. 

DVOBC Pixel Clock Input: When selected as the dot clock PLL 

(DPLL) reference input, this clock reference input supports SSC 

clocking for DVO LVDS devices. 

DVOBC Interrupt: When configured as an interrupt input, this 

interrupt can support either DVOB or DVOC. 

DVOBCCLKINT needs to be pulled down if the signal is NOT 

used. 

Display Power Management Signaling: This signal is used only in 

mobile systems to act as the DREFCLK in certain power 

management states(i.e. Display Power Down Mode); DPMS Clock 

is used to refresh video during S1-M. Clock Chip is powered down 

in S1-M. DPMS should come from a clock source that runs during 

DREFCLK I Display Clock Input: This pin is used to provide a 48-MHz input 

LVTTL clock to the Display PLL that is used for 2D/Video and DAC. 

LVDS LCK Flat Panel Clocking 

DREFSSCLK I 

LVTTL 

Display SSC Clock Input: This pin provides a 48-MHz or 66-MHz 

input clock (SSC or non-SSC) to the Display PLL B. 

Dedicated LVDS LCD Flat Panel Interface Signals 

Signal Name Type Voltage Description 

ICLKAP O 1.25 V± Channel A differential clock pair output (true): 245-800 MHz 

LVDS 225 mV 

ICLKAM O 1.25 V± Channel A differential clock pair output (compliment): 

LVDS 225 mV 245-800 MHz. 

IYAP[3:0] O 1.25 V± Channel A differential data pair 3:0 output (true): 245-800 

LVDS 225 mV MHz. 

IYAM[3:0] O 1.25 V± Channel A differential data pair 3:0 output (compliment): 

LVDS 225 mV 245-800 MHz. 

86



Dedicated LVDS LCD Flat Panel Interface Signals (Continued) 

Signal Name Type Voltage Description 

ICLKBP O 1.25 V± Channel B differential clock pair output (true): 245-800 MHz. 

LVDS 225 mV 

ICLKBM O 1.25 V± Channel B differential clock pair output (compliment): 245- 

LVDS 225 mV 800 MHz. 

IYBP[3:0] O 1.25 V± Channel B differential data pair 3:0 output (true): 245-800 

LVDS 225 mV MHz. 

IYBM[3:0] O 1.25 V± Channel B differential data pair 3:0 output (compliment): 

LVDS 225 mV 245-800 MHz. 

Digital Video Output B (DVOB) Port Signals 


DVOBD[11:0] O 

DVO 

DVOBHSYNC O 

DVO 

DVOBVSYNC O 

DVO 

DVOBBLANK# O 

DVO 

DVOBFLDSTL I 

DVO 

DVOB Data: This data bus is used to drive 12-bit RGB data on 

each edge of the differential clock signals, DVOBCLK and 

DVOBCLK#. This provides 24-bits of data per clock period. In dual 

channel mode, this provides the lower 12-bits of pixel data. 

DVOBD[11:0] should be left as left as NC (“Not Connected”) if not 

used. 

Horizontal Sync: HSYNC signal for the DVOB interface. 

DVOBHSYNC should be left as left as NC (“Not Connected”) if 

not used. 

Vertical Sync: VSYNC signal for the DVOB interface. 

DVOBVSYNC should be left as left as NC (“Not Connected”) if the 

signal is NOT used when using internal graphics device. 

Flicker Blank or Border Period Indication: DVOBBLANK# is a 

programmable output pin driven by the GMCH. 

When programmed as a blank period indication, this pin indicates 

active pixels excluding the border. When programmed as a border 

period indication, this pin indicates active pixel including the border 

pixels. 

DVOBBLANK# should be left as left as NC (“Not Connected”) if 

not used. 

TV Field and Flat Panel Stall Signal. This input can be 

programmed to be either a TV Field input from the TV encoder or 

Stall input from the flat panel. 

DVOB TV Field Signal: When used as a Field input, it synchronizes 

the overlay field with the TV encoder field when the overlay is 

displaying an interleaved source. 

DVOB Flat Panel Stall Signal: When used as the Stall input, it 

indicates that the pixel pipeline should stall one horizontal line. The 

signal changes during horizontal blanking. The panel fitting logic, 

when expanding the image vertically, uses this. 

DVOBFLDSTL needs to be pulled down if not used. 

Digital Video Output C (DVOC) Port Signals 


DVOCD[11:0] O 

DVO 

DVOCHSYNC O 

DVO 

DVOCVSYNC O 

DVO 

DVOCBLANK# O 

DVO 

DVOCFLDSTL I 

DVO 

DVOC Data: This data bus is used to drive 12-bit RGB data on 

each edge of the differential clock signals, DVOCCLK and 

DVOCCLK#. This provides 24-bits of data per clock period. In dual 

channel mode, this provides the upper 12-bits of pixel data. 

DVOCD[11:0] should be left as left as NC (“Not Connected”) if not 

used. 

Horizontal Sync: HSYNC signal for the DVOC interface. 

DVOCHSYNC should be left as left as NC (“Not Connected”) if 

not used. 

Vertical Sync: VSYNC signal for the DVOC interface. 

DVOCVSYNC should be left as left as NC (“Not Connected”) if the 

signal is NOT used when using internal graphics device. 

Flicker Blank or Border Period Indication: DVOCBLANK# is a 

programmable output pin driven by the GMCH. 

When programmed as a blank period indication, this pin indicates 

active pixels excluding the border. When programmed as a border 

period indication, this pin indicates active pixel including the border 

pixels. 

DVOCBLANK# should be left as left as NC (“Not Connected”) if 

not used. 

TV Field and Flat Panel Stall Signal. This input can be 

programmed to be either a TV Field input from the TV encoder or 

Stall input from the flat panel. 

DVOC TV Field Signal: When used as a Field input, it synchronizes 

the overlay field with the TV encoder field when the overlay is 

displaying an interleaved source. 

DVOC Flat Panel Stall Signal: When used as the Stall input, it 

indicates that the pixel pipeline should stall one horizontal line. The 

signal changes during horizontal blanking. The panel fitting logic, 

when expanding the image vertically, uses this. 

DVOCFLDSTL needs to be pulled down if not used. 

DVOB and DVOC Port Common Signals 


DVOBCINTR# I 

DVO 

ADDID[7:0] I 

DVO 

DVODETECT I 

DVO 

DVOBC Interrupt: This pin is used to signal an interrupt, typically 

used to indicate a hot plug or unplug of a digital display. 

ADDID[7:0]: These pins are used to communicate to the Video 

BIOS when an external device is interfaced to the DVO port. 

Note: Bit[7] needs to be strapped low when an on-board DVO 

device is present. The other pins should be left as NC. 

DVODETECT: This strapping signal indicates to the GMCH 

whether a DVO device is present or not. When a DVO device is 

connected, then DVODETECT = 0. 

87



Analog CRT Display Signals 


VSYNC O CRT Vertical Synchronization: This signal is used as the vertical 

CMOS sync signal. 

HSYNC O CRT Horizontal Synchronization: This signal is used as the 

CMOS horizontal sync signal. 

RED O Red (Analog Video Output): This signal is a CRT Analog video 

Analog output from the internal color palette DAC. The DAC is designed 

for a 37.5-ohm equivalent load on each pin (e.g., 75-ohm resistor on 

the board, in parallel with the 75-ohm. CRT load). 

RED# O 

Analog 

Red# (Analog Output): Tied to ground. 

GREEN O Green (Analog Video Output): This signal is a CRT analog video 


for a 37.5-ohm equivalent load on each pin (e.g., 75-ohm resistor on 

the board, in parallel with the 75-ohm . CRT load). 

GREEN# O 

Analog 

Green# (Analog Output): Tied to ground. 

BLUE O Blue (Analog Video Output) : This signal is a CRT Analog video 


for a 37.5-ohm equivalent load on each pin (e.g., 75- ohm resistor 

on the board, in parallel with the 75-ohm. CRT load). 

BLUE# O 

Analog 

Blue# (Analog Output): Tied to ground. 

GPIO Signals 

GPIO I/F Total Type Comments 

RSTIN# I 

CMOS 

PWROK I 

CMOS 

AGPBUSY# O 

CMOS 

EXTTS_0 I 

CMOS 

Reset: Primary Reset, Connected to PCIRST# of ICH4-M. 

Power OK: Indicates that power to GMCH is stable. 

AGPBUSY: Output of the GMCH IGD to the ICH4-M, which 

indicates that certain graphics activity is taking place. It will 

indicate to the ACPI software not to enter the C3 state. It will also 

cause a C3/C4 exit if C3/C4 was being entered, or was already 

entered when AGPBUSY# went active. Not active when the IGD is 

in any ACPI state other than D0. 

External Thermal Sensor Input: This signal is an active low input 

to the GMCH and is used to monitor the thermal condition around 

the System Memory and is used for triggering a read throttle. The 

GMCH can be optionally programmed to send a SERR, SCI, or SMI 

message to the ICH4-M upon the triggering of this signal. 

GPIO I/F Total Type Comments 

LCLKCTLA O SSC Chip Clock Control: Can be used to control an external clock 

CMOS chip with SSC control. 

LCLKCTLB O SSC Chip Data Control: Can be used to control an external clock 

CMOS chip for SSC control. 

PANELVDDEN O LVDS LCD Flat Panel Power Control: This signal is used enable 

CMOS power to the panel interface. 

PANELBKLTEN O LVDS LCD Flat Panel Backlight Enable: This signal is used to 

CMOS enable the backlight inverter (BLI). 

PANELBKLTCTL O LVDS LCD Flat Panel Backlight Brightness Control: This signal 

CMOS is used as the Pulse Width Modulated (PWM) control signal to 

control the backlight inverter. 

DDCACLK I/O CRT DDC Clock: This signal is used as the DDC clock signal 

CMOS between the CRT monitor and the GMCH. 

DDCADATA I/O CRT DDC Data: This signal is used as the DDC data signal 

CMOS between the CRT monitor and the GMCH. 

DDCPCLK I/O Panel DDC Clock: This signal is used as the DDC clock signal 

CMOS between the LFP and the GMCH. 

DDCPADATA I/O Panel DDC Data: This signal is used as the DDC data signal 

CMOS between the LFP and the GMCH. 

MI2CCLK I/O DVO I2C Clock: This signal is used as the I2C_CLK for a digital 

DVO display (i.e. TV-Out Encoder, TMDS transmitter). This signal is 

tri-stated during a hard reset. 

MI2CDATA I/O DVO I2C Data: This signal is used as the I2C_DATA for a digital 

DVO display (i.e. TV-Out Encoder, TMDS transmitter). This signal is 


MDVICLK I/O DVI DDC Clock: This signal is used as the DDC clock for a digital 

DVO display connector (i.e. primary digital monitor). This signal is 


MDVIDATA I/O DVI DDC Data: The signal is used as the DDC data for a digital 

DVO display connector (i.e. primary digital monitor). This signal is 


MDDCDATA I/O DVI DDC Clock: The signal is used as the DDC data for a digital 

DVO display connector (i.e. secondary digital monitor). This signal is 


MDDCCLK I/O DVI DDC Data: The signal is used as the DDC clock for a digital 

DVO display connector (i.e. secondary digital monitor). This signal is 


88



Voltage Reference, PLL Power Signals 


Host Processor 

HXRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. 

HYRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. 

HXSWING Analog Host Voltage Swing (RCOMP reference voltage): These signals 

provide a reference voltage used by the PSB RCOMP circuit. 

HYSWING Analog Host Voltage Swing (RCOMP reference voltage): These signals 

HDVREF[2:0] Ref 

Analog 

HAVREF Ref 

Analog 

HCCVREF Ref 

Analog 

provide a reference voltage used by the PSB RCOMP circuit. 

Host Data (input buffer) VREF: Reference voltage input for the 

data signals of the Host AGTL+ Interface. Input buffer differential 

amplifier to determine a high versus low input voltage. 

Host Address (input buffer) VREF: Reference voltage input for 

the address signals of the Host AGTL+ Interface. This signal is 

connected to the input buffer differential amplifier to determine a 

high versus low input voltage. 

Host Common Clock (Command input buffer) VREF: Reference 

voltage input for the common clock signals of the Host AGTL+ 

Interface. This signal is connected to the input buffer differential 

amplifier to determine a high versus low input voltage. 

VTTLF Power PSB Power Supply: VTTLF is the low frequency connection from 

the board. This signal is the primary connection of power for 

GMCH. 

VTTHF Power PSB Power Supply: VTTHF is the high frequency supply. It is for 

direct connection from an internal package plane to a capacitor 

placed immediately adjacent to the GMCH. 

NOTE: Not to be connected to power rail. 

System Memory 

SMRCOMP Analog System Memory RCOMP: This signal is used to calibrate the 

memory I/O buffers. 

SMVREF_0 Ref Memory Reference Voltage(Input buffer VREF):Reference 

Analog voltage input for Memory Interface. 

Input buffer differential amplifier to determine a high versus low 

input voltage. 

SMVSWINGH Ref RCOMP reference voltage: This is connected to the RCOMP 

Analog buffer differential amplifier and is used to calibrate the I/O buffers. 

SMVSWINGL Ref RCOMP reference voltage: This is connected to the RCOMP 

Analog buffer differential amplifier and is used to calibrate the I/O buffers. 

VCCSM Power Power supply for Memory I/O. 

VCCQSM Power Power supply for System Memory clock buffers. 

VCCASM Power Power supply for System Memory logic running at the core voltage 

(isolated supply, not connected to the core). 


Hub Interface 

HLRCOMP Analog Hub Interface RCOMP: This signal is connected to a reference 

resistor in order to calibrate the buffers. 

PSWING Ref Input buffer VREF: Input buffer differential amplifier to determine 

Analog a high versus low input voltage. 

VCCHL Power Power supply for Hub Interface buffers 

DVO 

DVORCOMP Analog Compensation for DVO: This signal is used to calibrate the DVO 

I/O buffers. 

GVREF Ref Input buffer VREF: Input buffer differential amplifier to determine 

Analog a high versus low input voltage. 

VCCDVO Power Power supply for DVO. 

GPIO 

VCCGPIO Power Power supply for GPIO buffers 

DAC 

REFSET Ref 

Analog 

Resistor Set: Set point resistor for the internal color palette DAC. 

VCCADAC Power Power supply for the DAC 

VSSADAC Power Ground supply for the DAC 

LVDS 

LIBG Analog LVDS reference current: signal connected to reference resistor. 

VCCDLVDS Power Digital power supply. 

VCCTXLVDS Power Data/Clk Tx power supply. 

VCCALVDS Power Analog power supply. 

VSSALVDS Power Ground supply for LVDS. 

Clocks 

VCCAHPLL Power Power supply for the Host PLL. 

VCCAGPLL Power Power supply for the Hub/DVO PLL. 

VCCADPLLA Power Power supply for the display PLL A. 

VCCADPLLB Power Power supply for the display PLL B. 

Core 

VCC Power Power supply for the core. 

VSS Power Ground supply for the chip. 

89


5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) 

Hub Interface Signals 


HI[11:0] I/O Hub Interface Signals 

HI_STB/HI_STBS I/O Hub Interface Strobe/ Hub Interface Strobe Second: One of two 

differential strobe signals used to transmit and receive data through 

the hub interface. 

Hub Interface 1.5 mode this signal is not differential and is the 

HI_STB#/ 

HI_STBF 

second of the two strobe signals. 

I/O Hub Interface Strobe Complement / Hub Interface Strobe First: 

One of two differential strobe signals used to transmit and receive 

data through the hub interface. 

Hub Interface 1.5 mode this signal is not differential and is the first 

of the two strobe signals. 

HICOMP I/O Hub Interface Compensation: Used for hub interface buffer 

compensation. 

HI_VSWING I Hub Interface Voltage Swing: Analog input used to control the 

voltage swing and impedance strength of hub interface pins. 

LAN Connect Interface Signals 


LAN_CLK I LAN I/F Clock: Driven by the LAN Connect component. 

Frequency range is 5 MHz to 50 MHz. 

LAN_RXD[2:0] I Received Data: The LAN Connect component uses these signals to 

transfer data and control information to the integrated LAN 

Controller. These signals have integrated weak pull-up resistors. 

LAN_TXD[2:0] O Transmit Data: The integrated LAN Controller uses these signals 

to transfer data and control information to the LAN Connect 

component. 

LAN_RSTSYNC O LAN Reset/Sync: The LAN Connect component’s Reset and Sync 

signals are multiplexed onto this pin. 

EEPROM Interface Signals 


EE_SHCLK O EEPROM Shift Clock: Serial shift clock output to the EEPROM. 

EE_DIN I EEPROM Data In: Transfers data from the EEPROM to the ICH3. 

This signal has an integrated pull-up resistor. 

EE_DOUT O EEPROM Data Out: Transfers data from the ICH3 to the 

EEPROM. 

EE_CS O EEPROM Chip Select: Chip select signal to the EEPROM. 

Firmware Hub Interface Signals 


FWH[3:0]/ 

LAD[3:0] 

FWH[4]/ 

LFRAME# 

I/O Firmware Hub Signals. Muxed with LPC address signals. 

I/O LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME# 

signal. 

PCI Interface Signals 


AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data 

bus. During the first clock of a transaction, AD[31:0] contain a 

physical address (32 bits). During subsequent clocks, AD[31:0] 

contain data. The ICH4 drives all 0s on AD[31:0] during the address 

phase of all PCI Special Cycles. 

C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable 

signals are multiplexed on the same PCI pins. During the address 

phase of a transaction, C/BE[3:0]# define the bus command. During 

the data phase, C/BE[3:0]# define the Byte Enables. 

C/BE[3:0]# Command Type 

0 0 0 0 Interrupt Acknowledge 

0 0 0 1 Special Cycle 

0 0 1 0 I/O Read 

0 0 1 1 I/O Write 

0 1 1 0 Memory Read 

0 1 1 1 Memory Write 

1 0 1 0 Configuration Read 

1 0 1 1 Configuration Write 

1 1 0 0 Memory Read Multiple 

1 1 1 0 Memory Read Line 

1 1 1 1 Memory Write and Invalidate 

All command encodings not shown are reserved. The ICH4 does not 

decode reserved values, and therefore will not respond if a PCI 

master generates a cycle using one of the reserved values. 

DEVSEL# I/O Device Select: The ICH4 asserts DEVSEL# to claim a PCI 

transaction. As an output, the ICH4 asserts DEVSEL# when a PCI 

master peripheral attempts an access to an internal ICH4 address or 

an address destined for the hub interface (main memory or AGP). 

As an input, DEVSEL# indicates the response to an ICH4-initiated 

transaction on the PCI bus. DEVSEL# is tri-stated from the leading 

edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until 

driven by a Target device. 

90



PCI Interface Signals (Continued) 


FRAME# I/O Cycle Frame: The current Initiator drives FRAME# to indicate the 

beginning and duration of a PCI transaction. While the Initiator 

asserts FRAME#, data transfers continue. When the Initiator 

negates FRAME#, the transaction is in the final data phase. 

FRAME# is an input to the ICH4 when the ICH4 is the Target, and 

FRAME# is an output from the ICH4 when the ICH4 is the Initiator. 

FRAME# remains tri- stated by the ICH4 until driven by an 

Initiator. 

IRDY# I/O Initiator Ready: IRDY# indicates the ICH4's ability, as an 

Initiator, to complete the current data phase of the transaction. It is 

used in conjunction with TRDY#. A data phase is completed on any 

clock that both IRDY# and TRDY# are sampled asserted. During a 

write, IRDY# indicates the ICH4 has valid data present on 

AD[31:0]. During a read, it indicates the ICH4 is prepared to latch 

data. IRDY# is an input to the ICH4 when the ICH4 is the Target 

and an output from the ICH4 when the ICH4 is an Initiator. IRDY# 

remains tri-stated by the ICH4 until driven by an Initiator. 

TRDY# I/O Target Ready: TRDY# indicates the ICH4's ability, as a Target, to 

complete the current data phase of the transaction. TRDY# is used 

in conjunction with IRDY#. A data phase is completed when both 

TRDY# and IRDY# are sampled asserted. 

During a read, TRDY# indicates that the ICH4, as a Target, has 

placed valid data on AD[31:0]. During a write, TRDY# indicates 

that the ICH4, as a Target, is prepared to latch data. TRDY# is an 

input to the ICH4 when the ICH4 is the Initiator and an output from 

the ICH4 when the ICH4 is a Target. TRDY# is tri-stated from the 

leading edge of PCIRST#. TRDY# remains tri-stated by the ICH4 

until driven by a target. 

PAR I/O Calculated/Checked Parity: PAR uses “even” parity calculated on 

36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the 

ICH4 counts the number of 1s within the 36 bits plus PAR and the 

sum is always even. The ICH4 always calculates PAR on 36 bits 

regardless of the valid byte enables. The ICH4 generates PAR for 

address and data phases and only guarantees PAR to be valid one 

PCI clock after the corresponding address or data phase. The ICH4 

drives and tri-states PAR identically to the AD[31:0] lines except 

that the ICH4 delays PAR by exactly one PCI clock. PAR is an 

output during the address phase (delayed one clock) for all ICH4 

initiated transactions. PAR is an output during the data phase 

(delayed one clock) when the ICH4 is the Initiator of a PCI write 

transaction, and when it is the Target of a read transaction. ICH4 

checks parity when it is the Target of a PCI write transaction. If a 

parity error is detected, the ICH4 will set the appropriate internal 

status bits, and has the option to generate an NMI# or SMI#. 


STOP# I/O Stop: STOP# indicates that the ICH4, as a Target, is requesting the 

Initiator to stop the current transaction. STOP# causes the ICH4, as 

an Initiator, to stop the current transaction. STOP# is an output 

when the ICH4 is a Target and an input when the ICH4 is an 

Initiator. STOP# is tri-stated from the leading edge of PCIRST#. 

STOP# remains tri-stated until driven by the ICH4. 

PERR# I/O Parity Error: An external PCI device drives PERR# when it 

receives data that has a parity error. The ICH4 drives PERR# when 

it detects a parity error. The ICH4 can either generate an NMI# or 

SMI# upon detecting a parity error (either detected internally or 

REQ[4:0]# 

REQ[5]#/ 

REQ[B]#/ 

GPIO[1] 

GNT[4:0]# 

GNT[5]#/ 

GNT[B]#/ 

GPIO[17] 

reported via the PERR# signal). 

I PCI Requests: The ICH4 supports up to 6 masters on the PCI bus. 

REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the 

other, but not both). If not used for PCI or PC/PCI, 

REQ[5]#/REQ[B]# can instead be used as GPIO[1]. 

NOTE: REQ[0]# is programmable to have improved arbitration 

latency for for supporting PCI-based 1394 controllers. 

O PCI Grants: The ICH4 supports up to 6 masters on the PCI bus. 

GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the 

other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can 

instead be used as a GPIO. 

Pull-up resistors are not required on these signals. If pull-ups are 

used, they should be tied to the Vcc3_3 power rail. 

GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up. 

PCICLK I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for 

all transactions on the PCI Bus. 

NOTE: This clock does not stop based on STP_PCI# signal. 

PCICLK only stops based on SLP_S1# or SLP_S3#. 

PCIRST# O PCI Reset: ICH4 asserts PCIRST# to reset devices that reside on 

the PCI bus. The ICH4 asserts PCIRST# during power-up and when 

S/W initiates a hard reset sequence through the RC (CF9h) register. 

The ICH4 drives PCIRST# inactive a minimum of 1 ms after 

PWROK is driven active. The ICH4 drives PCIRST# active 

a minimum of 1 ms when initiated through the RC register. 

PLOCK# I/O PCI Lock: This signal indicates an exclusive bus operation and 

may require multiple transactions to complete. ICH4 asserts 

PLOCK# when it performs non- exclusive transactions on the PCI 

bus. Devices on the PCI bus (other than the ICH4) are not permitted 

to assert the PLOCK# signal. 

SERR# I/OD System Error: SERR# can be pulsed active by any PCI device that 

detects a system error condition. Upon sampling SERR# active, the 

ICH4 has the ability to generate an NMI, SMI#, or interrupt. 

91



PCI Interface Signals (Continued) 


PME# I/OD PCI Power Management Event: PCI peripherals drive PME# to 

wake the system from low-power states S1-M–S5. PME# assertion 

can also be enabled to generate an SCI from the S0 state. In some 

cases the ICH4 may drive PME# active due to an internal wake 

event. The ICH4 will not drive PME# high, but it will be pulled up 

to VccSus3_3 by an internal pull-up resistor. 

CLKRUN# I/O PCI Clock Run: Used to support PCI Clock Run protocol. 

Connects to PCI devices that need to request clock re-start, or 

prevention of clock stopping. 

REQ[A]#/ 

GPIO[0] 

REQ[B]#/ 

REQ[5]#/ 

GPIO[1] 

GNT[A]#/ 

GPIO[16] 

GNT[B]#/ 

GNT[5]#/ 

GPIO[17] 

NOTE: An external pull-up to the core power plane is required. 

I PC/PCI DMA Request [A:B]: This request serializes ISA-like 

DMA Requests for the purpose of running ISA-compatible DMA 

cycles over the PCI bus. This is used by devices such as PCI based 

Super I/O or audio codecs which need to perform legacy 8237 DMA 

but have no ISA bus. 

When not used for PC/PCI requests, these signals can be used as 

General Purpose Inputs. REQ[B]# can instead be used as the 6th 

PCI bus request. 

O PC/PCI DMA Acknowledges [A: B]: This grant serializes an 

ISA-like DACK# for the purpose of running DMA/ISA Master 

cycles over the PCI bus. This is used by devices such as PCI based 

Super/IO or audio codecs which need to perform legacy 8237 DMA 

but have no ISA bus. 

When not used for PC/PCI, these signals can be used as General 

Purpose Outputs. GNTB# can also be used as the 6th PCI bus 

master grant output. These signal have internal pull-up resistors. 

IDE Interface Signals 


PDCS1#, SDCS1# O Primary and Secondary IDE Device Chip Selects for 100 Range: 

For ATA command register block. This output signal is connected 

to the corresponding signal on the primary or secondary IDE 

connector. 

PDCS3#, SDCS3# O Primary and Secondary IDE Device Chip Select for 300 Range: 

For ATA control register block. This output signal is connected to 

the corresponding signal on the primary or secondary IDE 

PDA[2:0], 

SDA[2:0] 

connector. 

O Primary and Secondary IDE Device Address: These output 

signals are connected to the corresponding signals on the primary or 

secondary IDE connectors. They are used to indicate which byte in 

either the ATA command block or control block is being addressed. 


PDD[15:0], 

SDD[15:0] 

PDDREQ, 

SDDREQ 

PDDACK#, 

SDDACK# 

PDIOR#/ 

(PDWSTB/PRDMA 

RDY#) 

SDIOR#/ 

(SDWSTB/SRDMA 

RDY#) 

PDIOW#/ 

(PDSTOP) 

SDIOW#/ 

(SDSTOP) 

I/O Primary and Secondary IDE Device Data: These signals directly 

drive the corresponding signals on the primary or secondary IDE 

connector. There is a weak internal pull-down resistor on PDD[7] 

and SDD[7]. 

I Primary and Secondary IDE Device DMA Request: These input 

signals are directly driven from the DRQ signals on the primary or 

secondary IDE connector. It is asserted by the IDE device to request 

a data transfer, and used in conjunction with the PCI bus master IDE 

function and are not associated with any AT compatible DMA 

channel. There is a weak internal pull-down resistor on these 

signals. 

O Primary and Secondary IDE Device DMA Acknowledge: These 

signals directly drive the DAK# signals on the primary and 

secondary IDE connectors. Each is asserted by the ICH4 to indicate 

to IDE DMA slave devices that a given data transfer cycle (assertion 

of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is 

used in conjunction with the PCI bus master IDE function and are 

not associated with any AT-compatible DMA channel. 

O Primary and Secondary Disk I/O Read (PIO and Non-Ultra 

DMA): This is the command to the IDE device that it may drive 

data onto the PDD or SDD lines. Data is latched by the ICH4 on the 

deassertion edge of PDIOR# or SDIOR#. The IDE device is 

selected either by the ATA register file chip selects (PDCS1# or 

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the 

IDE DMA acknowledge (PDDAK# or SDDAK#). 

Primary and Secondary Disk Write Strobe (Ultra DMA Writes to 

Disk): This is the data write strobe for writes to disk. When writing 

to disk, ICH4 drives valid data on rising and falling edges of 

PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready 

(Ultra DMA Reads from Disk): This is the DMA ready for reads 

from disk. When reading from disk, ICH4 deasserts 

PRDMARDY# or SRDMARDY# to pause burst data transfers. 

O Primary and Secondary Disk I/O Write (PIO and Non-Ultra 

DMA): This is the command to the IDE device that it may latch 

data from the PDD or SDD lines. Data is latched by the IDE device 

on the deassertion edge of PDIOW# or SDIOW#. The IDE device is 

selected either by the ATA register file chip selects (PDCS1# or 

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the 

IDE DMA acknowledge (PDDAK# or SDDAK#). 

Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this 

signal to terminate a burst. 

92



IDE Interface Signals (Continued) 


PIORDY#/ 

(PDRSTB/PWDMA 

RDY#) 

SIORDY#/ 

(SDRSTB/SWDMA 

RDY#) 

I Primary and Secondary I/O Channel Ready (PIO): This signal 

will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# 

or SDIOW# on writes) longer than the minimum width. It adds wait 

states to PIO transfers. 

Primary and Secondary Disk Read Strobe (Ultra DMA Reads from 

Disk): When reading from disk, the ICH4 latches data on rising and 

falling edges of this signal from the disk. 

Primary and Secondary Disk DMA Ready (Ultra DMA Writes to 

Disk): When writing to disk, this is de-asserted by the disk to pause 

burst data transfers. 

Interrupt Signals 


SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt 

protocol. 

PIRQ[D:A]# I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals 

can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as 

described in the Interrupt Steering section. Each PIRQx# line has a 

separate Route Control Register. 

In APIC mode, these signals are connected to the internal I/O APIC 

in the following fashion: PIRQ[A]# is connected to IRQ16, 

PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. 

PIRQ[H:E]#/ 

GPIO[5:2] 

This frees the legacy interrupts. 

I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals 

can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as 

described in the Interrupt Steering section. Each PIRQx# line has a 

separate Route Control Register. 

In APIC mode, these signals are connected to the internal I/O APIC 

in the following fashion: PIRQ[E]# is connected to IRQ20, 

PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. 

This frees the legacy interrupts. If not needed for interrupts, these 

signals can be used as GPIO. 

IRQ[14:15] I Interrupt Request 14:15: These interrupt inputs are connected to 

the IDE drives. IRQ14 is used by the drives connected to the 

Primary controller and IRQ15 is used by the drives connected to the 

Secondary controller. 

APICCLK I APIC Clock: This clock operates up to 33.33 MHz. 

APICD[1:0] I/OD APIC Data: These bi-directional open drain signals are used to 

send and receive data over the APIC bus. As inputs the data is valid 

on the rising edge of APICCLK. As outputs, new data is driven 

from the rising edge of the APICCLK. 

LPC Interface Signals 


LAD[3:0]/ 

I/O LPC Multiplexed Command, Address, Data: For the LAD[3:0] 

FWH[3:0] 

signals, internal pull-ups are provided. 

LFRAME#/ 

O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an 

FWH[4] 

abort. 

LDRQ[1:0]# I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used 

to request DMA or bus master access. These signals are typically 

connected to an external Super I/O device. An internal pull-up 

resistor is provided on these signals. 

USB Interface Signals 


USBP0P, 

USBP0N, 

USBP1P, 

USBP1N 

USBP2P, 

USBP2N, 

USBP3P, 

USBP3N 

USBP4P, 

USBP4N, 

USBP5P, 

USBP4N 

I/O Universal Serial Bus Port 1:0 Differential: These differential 

pairs are used to transmit data/address/command signals for ports 0 

and 1. These ports can be routed to USB UHCI Controller #1 or the 

USB EHCI Controller. 

NOTE: No external resistors are required on these signals. The 

ICH4 integrates 15 k . pull-downs and provides an output driver 

impedance of 45 . which requires no external series resistor 




USB EHCI Controller. 



impedance of 45 . which requires no external series resistor. 




USB EHCI Controller 



impedance of 45 . which requires no external series resistor 

OC[5:0]# I/O Overcurrent Indicators: These signals set corresponding bits in 

the USB controllers to indicate that an overcurrent condition has 

occurred. 

USBRBIAS O USB Resistor Bias: Analog connection point for an external 

resistor to ground. USBRBIAS should be connected to 

USBRBIAS# as close to the resistor as possible. 

USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an 

external resistor to ground. USBRBIAS# should be connected to 

USBRBIAS as close to the resistor as possible. 

93



Power Management Interface Signals 


THRM# I Thermal Alarm: This is an active low signal generated by external 

hardware to start the hardware clock throttling mode. The signal can 

also generate an SMI# or an SCI. 

THRMTRIP# I Thermal Trip: When low, THRMTRIP# indicates that a thermal 

trip from the processor occurred; the ICH4 will immediately 

transition to a S5 state. The ICH4 will not wait for the processor 

stop grant cycle since the processor has overheated. 

SLP_S1# O S1 Sleep Control: SLP_S1# provides Clock Synthesizer or Power 

plane control. Optional use is to shut off power to non-critical 

systems when in the S1- M (Powered On Suspend), S3 (Suspend To 

RAM), S4 (Suspend to Disk) or S5 (Soft Off) states. 

SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. It shuts off 

power to all non-critical systems when in S3 (Suspend To RAM), 

S4 (Suspend to Disk), or S5 (Soft Off) states. 

SLP_S4# O S4 Sleep Control: SLP_S4# is for power plane control. It shuts 

power to all non-critical systems when in the S4 (Suspend to Disk) 

or S5 (Soft Off) state. 

SLP_S5# O S5 Sleep Control: SLP_S5# is for power plane control. The signal 

is used to shut power off to all non-critical systems when in the S5 

(Soft Off) states. 

PWROK I Power OK: When asserted, PWROK is an indication to the ICH4 

that core power and PCICLK have been stable for at least 1 ms. 

PWROK can be driven asynchronously. When PWROK is negated, 

the ICH4 asserts PCIRST#. 

NOTE: PWROK must deassert for a minimum of 3 RTC clock 

periods for the ICH4 to fully reset the power and properly generate 

the PCIRST# output 

PWRBTN# I Power Button: The Power Button causes SMI# or SCI to indicate a 

system request to go to a sleep state. If the system is already in a 

sleep state, this signal causes a wake event. If PWRBTN# is pressed 

for more than 4 seconds, this causes an unconditional transition 

(power button override) to the S5 state with only the PWRBTN# 

available as a wake event. Override occurs even if the system is in 

the S1-M–S4 states. This signal has an internal pull-up resistor. 

RI# I Ring Indicate: This signal is an input from the modem interface. It 

can be enabled as a wake event, and this is preserved across power 

failures. 

SYS_RESET# I System Reset: This pin forces an internal reset after being 

debounced. The ICH4 will reset immediately if the SMBus is idle; 

otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle 

before forcing a reset on the system. 

RSMRST# I Resume Well Reset: This signal is used for resetting the resume 

power plane logic. 


LAN_RST# I LAN Reset: This signal must be asserted at least 10 ms after the 

resume well power (VccLAN3_3 and VccLAN1_5 is valid. When 

deasserted, this signal is an indication that the resume well power is 

SUS_STAT#/ 

LPCPD# 

stable. 

O Suspend Status: This signal is asserted by the ICH4 to indicate that 

the system will be entering a low power state soon. This can be 

monitored by devices with memory that need to switch from normal 

refresh to suspend refresh mode. It can also be used by other 

peripherals as an indication that they should isolate their outputs 

that may be going to powered-off planes. This signal is called 

LPCPD# on the LPC I/F. 

C3_STAT# O C3_STAT#: This signal will typically be configured as C3_STAT#. 

It is used for indicating to an AGP device that a C3 state transition 

is beginning or ending. If C3_STAT# functionality is not required, 

this signal may be used as a GPO. 

NOTE: This signal will be asserted in S1-M on the ICH4-M. 

SUSCLK O Suspend Clock: Output of the RTC generator circuit to use by other 

chips for refresh clock. 

AGPBUSY# I AGP Bus Busy: To support the C3 state. This signal is an 

indication that the AGP device is busy. When this signal is asserted, 

the BM_STS bit will be set. If this functionality is not needed, this 

signal may be configured as a GPI. 

STP_PCI# O Stop PCI Clock: This signal is an output to the external clock 

generator for it to turn off the PCI clock. Used to support PCI 

CLKRUN# protocol. If this functionality is not needed, This signal 

can be configured as a GPO. 

STP_CPU# O Stop CPU Clock: Output to the external clock generator for it to 

turn off the processor clock. Used to support the C3 state. If this 

functionality is not needed, this signal can be configured as a GPO. 

BATLOW# I Battery Low: This signal is an input from the battery to indicate 

that there is insufficient power to boot the system. Assertion will 

prevent wake from S1-M–S5 state. Can also be enabled to cause an 

SMI# when asserted. 

CPUPERF# OD CPU Performance: CPUPERF# is used for Intel SpeedStep 

technology support. The signal selects which power state to put the 

processor in. 

SSMUXSEL O SpeedStep Mux Select: SSMUXSEL is used for Intel SpeedStep 

technology support. The signal selects the voltage level for the 

VGATE/ 

VRMPWRGD 

processor. 

I VGATE/VRM Power Good: VGATE/VRMPWRGD is used for 

Intel SpeedStep technology support. This is an output from the 

processor’s voltage regulator to indicate that the voltage is stable. 

This signal may go inactive during an Intel SpeedStep transition. 

94



Power Management Interface Signals (Continued) 


DPRSLPVR O Deeper Sleep - Voltage Regulator: This signal is used to lower the 

voltage of VRM during C4 and S1-M states. When the signal is 

high, the voltage regulator outputs the lower “Deeper Sleep” 

voltage. When the signal is low (default), the voltage regulator 

outputs the higher “Normal” voltage. During PCIRST#, the output 

driver is disabled and an internal pull-down is enabled. This is 

needed for implementing a strap on the pin. When PCIRST# 

deasserts, the output driver is enabled. To guarantee no glitches on 

the DPRSLPVR pin, the pull-down is disabled after the output 

driver is fully enabled. 

NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a 

functional strap. 

Processor Interface Signals 


A20M# O Mask A20: A20M# will go active based on either setting the 

appropriate bit in the Port 92h register, or based on the A20GATE 

input being active. 

Speed Strap: During the reset sequence, ICH4 drives A20M# high 

if the corresponding bit is set in the FREQ_STRP register. 

CPUSLP# O CPU Sleep: This signal puts the processor into a state that saves 

substantial power compared to Stop-Grant state. However, during 

that time, no snoops occur. The ICH4 can optionally assert the 

CPUSLP# signal when going to the S1-M state. 

FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor 

error signal on the processor. FERR# is only used if the ICH4 

coprocessor error reporting function is enabled in the General 

Control Register (Device 31:Function 0, Offset D0, bit 13). If 

FERR# is asserted, the ICH4 generates an internal IRQ13 to its 

interrupt controller unit. It is also used to gate the IGNNE# signal to 

ensure that IGNNE# is not asserted to the processor unless FERR# 

is active. FERR# requires an external weak pull-up to ensure a high 

level when the coprocessor error function is disabled. 

NOTE: FERR# can be used in some states for notification by the 

processor of pending interrupt events. This functionality is 

independent of the General Control Register bit setting. 

INTR O CPU Interrupt: INTR is asserted by the ICH4 to signal the 

processor that an interrupt request is pending and needs to be 

serviced. It is an asynchronous output and normally driven low. 

Speed Strap: During the reset sequence, ICH4 drives INTR high if 

the corresponding bit is set in the FREQ_STRP register. 


IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error 

pin on the processor. IGNNE# is only used if the ICH4 coprocessor 

error reporting function is enabled in the General Control Register 

(Device 31:Function 0, Offset D0, bit 13). If FERR# is active, 

indicating a coprocessor error, a write to the Coprocessor Error 

Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains 

asserted until FERR# is negated. If FERR# is not asserted when the 

Coprocessor Error Register is written, the IGNNE# signal is not 

asserted. 

Speed Strap: During the reset sequence, ICH4 drives IGNNE# high 

if the corresponding bit is set in the FREQ_STRP register. 

INIT# O Initialization: INIT# is asserted by the ICH4 for 16 PCI clocks to 

reset the processor. ICH4 can be configured to support CPU BIST. 

In that case, INIT# will be active when PCIRST# is active. 

NMI O Non-Maskable Interrupt: NMI is used to force a non-Maskable 

interrupt to the processor. The ICH4 can generate an NMI when 

either SERR# or IOCHK# is asserted. The processor detects an NMI 

when it detects a rising edge on NMI. 

NMI is reset by setting the corresponding NMI source 

enable/disable bit in the NMI Status and Control Register. 

Speed Strap: During the reset sequence, ICH4 drives NMI high if 

the corresponding bit is set in the FREQ_STRP register. 

SMI# O System Management Interrupt: SMI# is an active low output 

synchronous to PCICLK. It is asserted by the ICH4 in response to 

one of many enabled hardware or software events. 

STPCLK# O Stop Clock Request: STPCLK# is an active low output 

synchronous to PCICLK. It is asserted by the ICH4 in response to 

one of many hardware or software events. When the processor 

samples STPCLK# asserted, it responds by stopping its internal 

clock. 

RCIN# I Keyboard Controller Reset CPU: The keyboard controller can 

generate INIT# to the processor. This saves the external OR gate 

with the ICH4’s other sources of INIT#. When the ICH4 detects the 

assertion of this signal, INIT# is generated for 16 PCI clocks. 

NOTE: The ICH4 ignores RCIN# assertion during transitions to the 

S1-M, S3, S4 and S5 states. 

A20GATE I A20 Gate: A20GATE is from the keyboard controller. The signal 

acts as an alternative method to force the A20M# signal active. It 

saves the external OR gate needed with various other PCIsets. 

95



Processor Interface Signals (Continued) 


CPUPWRGD OD CPU Power Good: This signal should be connected to the 

processor’s PWRGOOD input. To allow for Intel ® SpeedStep 

technology support, this signal is kept high during an Intel 

SpeedStep technology state transition to prevent loss of processor 

context. This is an open-drain output signal (external pull-up 

resistor required) that represents a logical AND of the ICH4’s 

PWROK and VGATE / VRMPWRGD signals. 

DPSLP# O Deeper Sleep: This signal is asserted by the ICH4 to the processor. 

When the signal is low, the processor enters the Deeper Sleep state 

by gating off the processor Core clock inside the processor. When 

the signal is high (default), the processor is not in the Deeper Sleep 

state. This signal behaves identically to the STP_CPU# signal, but 

at the processor voltage level. 

SMBus Interface Signals 


SMBDATA I/OD SMBus Data: External pull-up is required. 

SMBCLK I/OD SMBus Clock: External pull-up is required. 

SMBALERT#/ 

GPIO[11] 

I SMBus Alert: This signal is used to wake the system or generate 

SMI#. If not used for SMBALERT#, it can be used as a GPI. 

System Management Interface Signals 


INTRUDER# I Intruder Detect: Can be set to disable system if box detected open. 

This signal’s status is readable, so it can be used like a GPI if the 

Intruder Detection is not needed. 

SMLINK[1:0] I/OD System Management Link: SMBus link to optional external 

system management ASIC or LAN controller. External pull-ups are 

required. 

Note that SMLINK[0] corresponds to an SMBus Clock signal, and 

SMLINK[1] corresponds to an SMBus Data signal. 

Real Time Clock Interface Signals 


RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal. 

RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. 

Other Clock Signals 


CLK14 I Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz. 

This clock is permitted to stop during S1-M (or lower) states. 

CLK48 I 48 MHz Clock: This clock is used to run the USB controller. It runs 

at 48 MHz. This clock is permitted to stop during S1-M (or lower) 

states. 

CLK66 I 66 MHz Clock: This is used to run the hub interface. It runs at 66 

MHz. This clock is permitted to stop during S1-M (or lower) states. 

Miscellaneous Signals 


SPKR O Speaker: The SPKR signal is the output of counter 2 and is 

internally “ANDed” with Port 61h bit 1 to provide Speaker Data 

Enable. This signal drives an external speaker driver device, which 

in turn drives the system speaker. Upon PCIRST#, its output state is 

0. 

NOTE: SPKR is sampled at the rising edge of PWROK as a 


RTCRST# I RTC Reset: When asserted, this signal resets register bits in the 

RTC well and sets the RTC_PWR_STS bit (bit 2 in 

GEN_PMCON3 register). 

NOTES: 

1. Clearing CMOS in an ICH4-based platform can be done by using 

a jumper on RTCRST# or GPI, or using SAFEMODE strap. 

Implementations should not attempt to clear CMOS by using a 

jumper to pull VccRTC low. 

2. Unless entering the XOR Chain Test Mode, the RTCRST# input 

must always be high when all other RTC power planes are on. 

96



AC’97 Link Signals 


AC_RST# O AC ’97 Reset: This signal is a master hardware reset to external 

Codec(s). 

AC_SYNC O AC ’97 Sync: This signal is a 48 kHz fixed rate sample sync to the 

Codec(s). 

AC_BIT_CLK I AC97 Bit Clock: This signal is a 12.288 MHz serial data clock 

generated by the external Codec(s). This signal has an integrated 

pull-down resistor. 

AC_SDOUT O AC97 Serial Data Out: Serial TDM data output to the Codec(s). 

NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a 


AC_SDIN[1:0] I AC97 Serial Data In 2:0: These signals are Serial TDM data inputs 

from the three Codecs. 

NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK 

Shutoff bit in the AC’97 Global Control Register is set to 1, or Both Function 5 and Function 6 of 

Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled. 

General Purpose I/O Signals 


GPIO[43:32] I/O Can be input or output. Main power well. 

GPIO[31:29] O Not implemented. 

GPIO[28:27] I/O Can be input or output. Resume power well. Unmuxed. 

GPIO[26] I/O Not implemented. 

GPIO[25] I/O Can be input or output. Resume power well. Unmuxed. 

GPIO[24:18] I/O Not Implemented in Mobile (Assign to native Functionality). 

GPIO[17:16] O Fixed as Output only. Main power well. Can be used instead as 

PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for 

PCI GNT[5]#. Integrated pull-up resistor. 

GPIO[15:14] I Not implemented. 

GPIO[13:12] I Fixed as Input only. Resume power well. Unmuxed. 

GPIO[11] I Fixed as Input only. Resume power well. Can be used instead as 

SMBALERT#. 

GPIO[10:9] I Not implemented. 

GPIO[8] I Fixed as Input only. Resume power well. Unmuxed. 

GPIO[7] I Fixed as Input only. Main power well. Unmuxed. 

GPIO[6] I Not Implemented in Mobile (Assign to Native Functionality) 

GPIO[5:2] I Fixed as Input only. Main power well. Can be used instead as 

PIRQ[E:H]#. 

GPIO[1:0] I Fixed as Input only. Main power well. Can be used instead as 

PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI 

REQ[5]#. 

NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO 

are not 5V tolerant. 

Power and Ground Signals 

Signal Name Description 

VCC3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 

or G3 states. 

VCC1_5 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 

states. 

VCCHI 1.5 V supply for Hub Interface 1.5 logic. 

1.8 V supply for Hub Interface 1.0 logic. 

This power may be shut off in S3, S4, S5 or G3 states. 

V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off in 

S3, S4, S5 or G3 states. 

HIREF Analog Input. Expected voltages are: 

0.9 V for HI 1.0 (Normal Hub Interface) Series Termination 

350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination 

This power is shut off in S3, S4, S5, and G3 states. 

VCCSUS3_3 3.3 V supply for resume well I/O buffers. This power is not expected to be shut 

off unless the main battery is removed or completely drained and AC power is 

not available. 

VCCSUS1_5 1.5 V supply for resume well logic. This power is not expected to be shut off 

unless the main battery is removed or completely drained and AC power is not 

available. 

V5REF_SUS Reference for 5 V tolerance on resume well inputs. This power is not expected 

to be shut off unless the main battery is removed or completely drained and AC 

power is not available. 

VCCLAN3_3 3.3 V supply for LAN Connect interface buffers. This is a separate power plane 

that may or may not be powered in S3–S5 states depending upon the presence or 

absence of AC power and network connectivity. This plane must be on in S0 and 

S1-M. 

VCCLAN1_5 1.5 V supply for LAN Controller logic. This is a separate power plane that may 

or may not be powered in S3–S5 states depending upon the presence or absence 

of AC power and network connectivity. This plane must be on in S0 and S1-M. 

VCCRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power 

is not expected to be shut off unless the RTC battery is removed or completely 

drained. 

NOTE: Implementations should not attempt to clear CMOS by using a jumper 

to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done 

by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. 

VCCPLL 1.5 V supply for core well logic. This signal is used for the USB PLL. This 

power may be shut off in S3, S4, S5 or G3 states. 

VBIAS RTC well bias voltage. The DC reference voltage applied to this pin sets a 

current that is mirrored throughout the oscillator and buffer circuitry. 

V_CPU_IO Powered by the same supply as the processor I/O voltage. This supply is used to 

drive the processor interface outputs. 

VSS Grounds. 

97

6. System Block Diagram 

U17 

CardBus & 

Card Reader 

CB710 

U21 

Power 

Switch 

PCMCIA 

Slot 

J520 

MINI PCI 

Card 

Reader 

Slot 

CRT Connector 

TFT Flat Panel 

TV S-Video 

U9 

1394 

Controller 

VT6307L 

1394a Port 


RGB 

LVDS 

U7 

CH7011A 

PCI Bus 

USB * 3 

HDD 

DVD-ROM 

U15 

LAN PHY 

VT6105LOM 

RJ-45 Jack 

DVOC 

IR Module 

Eight LED 

U501 

Intel Banais Processor 

Micro-FCPGA 

U502 

Memory Controller 

Hub 

Montara - GM 

U3 

I/O Controller Hub 

ICH4 - M 

Hub Link 

LPC 

U510 

Super I/O 

PC87393 

U19 

Flash ROM 

200/266MHz 

U1 

Thermal Sensor 

ADM1021A 

AC Link U509 

U511 

Audio Codec 

STAC9750 

Amplifier 

ISA Bus 

U504 

Micro 

Controller 

H8/F3437 

200 pin DDR SO-DIMM Socket * 2 

J6 

M.D.C 

External Microphone 

Internal Microphone 

Internal Speaker 

SPDIF Jack 

RJ-11 Jack (D/D Board) 

FAN 

Power Button 

Touch Pad 

Keyboard 

98

7. Maintenance Diagnostics 

7.1 Introduction 


Each time the computer is turned on, the system bios runs a series of internal checks on the hardware. This 

power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error 

messages of post can alert you to the problems of your computer. 

If an error is detected during these tests, you will see an error message displayed on the screen. If the error 

occurs before the display is initialized,then the screen cannot display the error message. Error codes or 

system beeps are used to identify a post error that occurs when the screen is not available. 

The value for the diagnostic port (378H) is written at the beginning of the test. Therefore, if the test failed, 

the user can determine where the problem occurred by reading the last value written to port 378H by the 

378H port debug board plug at PIO PORT. 

99

7.2 Error Codes 

Code 

10h 

11h 

12h 

13h 

14h 

15h 

16h 

17h 

18h 

19h 

1Ah 

1Bh 

1Ch 

1Dh 

1Eh 

1Fh 


Following is a list of error codes in sequent display on the PIO debug board. 

POST Routine Description 

Some type of lone reset 

Turn off FAST A20 for POST 

Signal power on reset 

Initialize the chipset 

Search for ISA Bus VGA adapter 

Reset counter / Timer 1 

User register config through CMOS 

Size memory 

Dispatch to RAM test 

Check sum the ROM 

Reset PIC’s 

Initialize video adapter(s) 

Initialize video (6845Regs) 

Initialize color adapter 

Initialize monochrome adapter 

Test 8237A page registers 

Code 

20h 

21h 

22h 

23h 

24h 

25h 

26h 

27h 

28h 

29h 

2Ah 

2Bh 

2Ch 

2Dh 

2Eh 

2Fh 


Test keyboard 

Test keyboard controller 

Check if CMOS RAM valid 

Test battery fail & CMOS X-SUM 

Test the DMA controller 

Initialize 8237A controller 

Initialize int vectors 

RAM quick sizing 

Protected mode entered safely 

RAM test completed 

Protected mode exit successful 

Setup shadow 

Going to initialize video 

Search for monochrome adapter 

Search for color adapter 

Sign on messages displayed 

100

7.2 Error Codes 

Code 

30h 

31h 

32h 

33h 

34h 

35h 

36h 

37h 

38h 

39h 

3Ah 

3Bh 

3Ch 

3Dh 

3Eh 

3Fh 


Following is a list of error codes in sequent display on the PIO debug board. 


Special init of keyboard ctlr 

Test if keyboard Present 

Test keyboard Interrupt 

Test keyboard command byte 

Test, blank and count all RAM 

Protected mode entered safely(2) 

RAM test complete 

Protected mode exit successful 

Update output port 

Setup cache controller 

Test if 18.2Hz periodic working 

Test for RTC ticking 

Initialize the hardware vectors 

Search and init the mouse 

Update NUMLOCK status 

Special init of COMM and LPT ports 

Code 

40h 

41h 

42h 

43h 

44h 

45h 

46h 

47h 

48h 

49h 

50h 

51h 

52h 


Configure the COMM and LPT ports 

Initialize the floppies 

Initialize the hard disk 

Initialize option ROMs 

OEM’s init of power management 

Update NUMLOCK status 

Test for coprocessor installed 

OEM functions before boot 

Dispatch to operate system boot 

Jump into bootstrap code 

ACPI init 

PM init & Geyserville 

USB HC init 

101

7.3 Debug Tool 


8080 MB would not support Parallel Port, then we could not plug the Debug Card to PIO Port to get the 

Port 378 error code. For this cause, 8080 MB have reserved eight LEDs that are parallel connection with 

PIO output lines (Figure 1), when the system BIOS write the error code to Port 378, the LEDs can show the 

messages. 

U510 

Super I/O 

PC87393 

D10-D17 

CL-190G 

Figure 1 

PIO_D[0:7] 

102

8. Trouble Shooting 

8.1 No Power 

8.2 No Display 

8.3 VGA Controller Failure LCD No Display 

8.4 External Monitor No Display 

8.5 Memory Test Error 

8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error 

8.7 Hard Driver Test Error 

8.8 CD-ROM Driver Test Error 

8.9 USB Port Test Error 

8.10 Audio Failure 

8.11 LAN Test Error 

8.12 PC Card & Card Reader Socket Failure 

8.13 IEEE1394 Failure 


103

8.1 No Power 

No Power 

Is the 

notebook connected 

to power (either AC adaptor 

or battery)? 

Power 

OK? 

Yes 

Try another known good 

battery or AC adapter. 

No 

Is the 

M/B and charger 

BD connected 

properly? 

No 

Try another known 

good charger BD. 


When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. 

Yes 

Yes 

No 

Connect AC adaptor 

or battery. 

Replace the faulty AC 

adaptor or Battery. 

Connect AC adaptor 

or battery. 

Power 

OK? 

Yes 

Replace the faulty 

Charger BD. 

No 

Board-level 

Troubleshooting 

Replace 

Motherboard 

Where from 

power source problem 

(first use AC to 

power it)? 

Battery 

AC 

Power 

Check following parts and signals: 

PJ501 

PF2 

PL2 

PL3 

PR24 

PQ5 

PD4 

PD5 

PD7 

PD503 

PL501 

PQ504 

PU1 

PL1 

PL8 

PF1 

PQ501 

PQ502 

Parts: Signals: 

ADINP 

DVMAIN 

PWR_VDDIN 

Check following parts and signals: 


BATT 

BAT_TEMP 

BAT_VOLT 

BAT_CLK 

BAT_DATA 

104

POWER IN 

PJ501 P23 

P22 

+5V_P 

8.1 No Power 

PF2,PL2 

PL3,PR24 

Q511 

PWR_VDDIN 



Main Voltage Map 

P23 

P22 

PD4 

H8_AVREF 

Q512 

P22 

VDD5 

PQ5 

F502,U506 

NOTE : 

P23 

PF2 

PD503,PL501,PL502,PQ504,PU1 

P23 

ADINP 

Charge 

PD5 

PD7 

Discharge 

P24 

BATT 

DVMAIN 

P23 

PQ501,PQ502 

Discharge 

P9 P9 

U516 D503 

VDD3_RTC 

RSM5V U5 

P22 

P22 

Q37 U6 

VDD3 

: Page 23 on M/B Board circuit diagram. 

: Through by part PF2. 

+VCC_RTC 

P22 

VDD1.5 

DD_CPU 

PL6,PL7 PU501,PU504~PU507,PU509,PL506,PR35 

PL509,PU502 PU17, PL510 ,PR62 

PL4,PU23 

PU16,PL508,PR59 

PU19, PL512, PR70 

PU18,PU503,PL514,PR71 

PU5 

PL515 

PL5,PU22 PU20,PU21,PL513 

P28 

+1.2V_P 

P28 

+1.05V_P 

P25 

+3V_P 

P27 

+1.25V_DDR_P 

P25 

+5V_P 

U25,JO45,JO46 

JO516 

P27 

+2.5V_DDR_P 

JO7 

JO513,JO514 

P29 

+VCC_CORE 

U27,JO48,JO49 

P22 

+3V 

P22 

+5V 

P22 

+1.25V_DDR_F 

JO39,JO41 

P22 

+1.2V 

P22 

+VCCP 

L7 

U14 

JO50 

P22 

+2.5V_DDR 

P3 

+VCCQ 

U21 

U21 

P18 

+VPPOUT 

P22 

+1.25V_DDR 

P18 

+CARD_VCC 

R185,R186 

L33 

L34 

PL517,PU14 

PL517,PU15 

P7 

+DDR_VREF 

P16 

+LAN_D2.5V 

P16 

+LAN_A2.5V 

P26 

+1.5V_P 

P26 

+1.8V_P 

JL1 

L9 

L517 

L14 

L513 

L19 

L21 

JO512 

JO511 

Q22,R310 

L24,U23 

L29,U24 

L31,JS4 

+3V_FIR 

P4 

+3VCLK66 

P4 

+3VCLKCPU 

P4 

+3VCLKANA 

P4 

+3VCLKPCI 

P15 

1394_AVCC 

P15 

1394_VCC 

P22 

+1.5V 

P22 

+1.8V 

P18 

+SDVDD 

P11 

+5V_HDD 

+5V_CDROM 

P12 

P11 

AVDDAD 

L6 

(D/D Board) 

P3 

+VCCA 

105

POWER IN 

P20 

U504 

PJ501 

Micro 

Controller 

H8/F3437 

8.1 No Power 

1 

2 

3 

39 

55 

30 

19 



+5V_P 

19 

PF2 

6.5A/32VDC 

I_LIMIT 

LEARNING 

ADEN# 

SW_VDD5 

SW_VDD5# 

PC9 

0.1µ 

Q511 

SI2301DS 

D S 

Q510 

DTC144WK 

G 

PL2 

120Z/100M 

PL3 

120Z/100M 

R622 

100K 

PC16 

1µ 

VDD5 

C616 

4.7µ 

PC11 

1µ 

PC23 

0.1µ 

PR18 

10 

PD2 

RLZ24D 

3 

4 

6 

PC18 

0.1µ 

VCC 

RS+ 

OUT 

JO3 

PR24 

.02 

PU3 

5 

RS- 

MAX4173FEUT 

PR30 

470K 

PR41 

1M 

3 

2 

1 

F502 

FUSE_1206 

PQ5 

SI4835DY 

S 

G 

D 

PR39 

100K 

PQ7 

2N7002 

8 

7 

6 

5 

PWR_VDDIN 

PR506 

324K 

ADINP 

PR37 

4.7K 

PR29 

4.7K 

PQ503 

DTC144WK 

PR508 

33K 

PD5 

SBM1040 

1,2 3 

PQ505 

2N7002 

PR507 

100K 

G 

S 

D 

3 

2 

1 

8 

7 

6 

5 

PC4 

0.01µ 

PD4 

BAV70LT1 

PQ501 

SI4835DY 

2 

1 

2 

1 

PD7 

BAV70LT1 

PWR_VDDIN H8_AVREF VDD5 VDD5 RSM5V RSM5V VDD3 

Q512 

SI2301DS 

S 

G 

D 

H8_AVREF 

PC569 

10µ 

SW_VDD5 

D504 

RLZ5.6B 

U506 

AMS3107 

1 

8 

OUTPUT P22 INPUT 

VDD5 

R378 

100K 

S 

Q38 

DTC144TKA 

Q37 

SI2301DS 

G 

R1 

D 

D27 

BAS32L 

RSM5V 

R379 

47K 

ADEN# 

VDD5 

RSM5V 

C140 

0.1µ 

3 

1 

R178 

2K 

VIN 

PC507 

0.1µ 

G 

GND/ADJ 

S 

D 

3 

3 

PC30 

1000P 

3 

2 

1 

8 

7 

6 

5 

R180 

10K 

PC501 

1000P 

U5 

AME1117 

P22 

VOUT 

PQ502 

SI4835DY 

2 

PWR_VDDIN 

DVMAIN 

VDD3 

BATT 

C141 

2.2µ 

106

ADINP 

CHARGING 

From H8 

8.1 No Power 

PD503 

B340LA 

G 



D 

S 

PC17 

1000P 

PL501 

120Z/100M 

PC503 

0.01µ 

PQ507 

2N7002 

PC13 

0.1µ 

PR12 

15K 

PC504 

0.01µ 

REF 

PL501 

FUSE_1206 

PQ508 

DTA144WK 

12 

VCC 

P24 

C1,C2 

13 

OUTPUTCTRL PU2 

5 

CT 

6 

RT 

14 

PC570 

10µ 

REF 

PR21 

10K 

2IN- 

15 

PR510 

4.7K 

8,11 

PWM 

TL594C 

PD505 

BAS32L 

PR509 

4.7K 

PQ506 

MMBT2222A 

2IN+ 

1IN- 

16 

2 

DTC 4 

FEEDBACK 

3 

PC24 

0.01µ 

PC21 

1µ 

PC19 

0.1µ 

PR511 

100K 

PR14 

100K 

3 

2 

1 

I_CTRL 

From H8 

2IN+ 

PQ504 

SI4835DY 

S 

4 

PR28 

6.19K 

PC26 

0.1µ 

G 

D 

8 

7 

6 

5 

PR31 

249K 

PR26 

2.49K 

PJS501 

PD504 

B340LA 

PL502 

33UH 

PC14 

0.1µ 

PR5 

130K 

PR10 

10K 

VDD5 

1.25V 3 

PR17 

3.3K 

2 

PQ4 

SCK431LCSK-5 

VDD5 

+ 

_ 

8 

4 

PC6 

0.1µ 

PR7 

10K 

2IN+ 

1 

PU4A 

LMV393M 

DVMAIN 

PR16 

787K 

PR6 

23.2K 

1.25V 5 

PC20 

0.1µ 

PR22 

100K 

PR3 

294K 

PR9 

4.7K 

PR11 

1M 

6 

+ 

_ 

8 

7 

PU1A 

SI4925DY 

LI_OVP 

VDD5 PR13 

100K 

8 

4 

CHARGING 

PC15 

150P 

7 

2 

PU4B 

LMV393M 

1 

3 

PR15 

100K 

PR19 

33K 

PQ3 

2N7002 

BATT_DEAD 

To H8 

PU1B 

SI4925DY 

4 

5 

6 

PD1 

RLZ20C 

BATT 

107

8.1 No Power 

P20 

U504 

Micro 

Controller 

H8/F3437 



42 

38 

99 

16 

2 

C260 

0.1µ 

R613 

4.7K 

VDD5 

3 

1 

D9 

BAV70LT1 

C261 

0.1µ 

VDD5 

R54 

4.7K 

BAT_TEMP 

BAT_VOLT 

BAT_CLK 

BAT_DATA 

R235 

2.2K 

R236 

2.2K 

R35 

33 

R612 

33 

BAT_T 

BAT_V 

BAT_C 

BAT_D 

BATT 

PC8 

0.1µ 

PR1 

301K 

PR8 

100K 

PR502 

0 

PR501 

0 

VDD5 

PR504 

4.99K 

PR503 

20K 

PD502 

BAV99 

VDD5 

2 

3 

1 

PL8 

120Z/100M 

PL1 

120Z/100M 

PC3 

0.1µ 

PC502 

0.1µ 

PC5 

0.1µ 

PD501 

BAV99 

VDD5 

2 

3 

1 

PF1 

6.5A/32VDC 

1,2 

5 

3 

4 

J501 

P23 

Battery Connector 

108



There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good. 

No Display 

Monitor 

or LCD module 

OK? 

Yes 

No 

Make sure that CPU module, 

DIMM memory are installed 

Properly. 

Display 

OK? 

No 

Yes 

1.Try another known good CPU module, 

DIMM module and BIOS. 

2.Remove all of I/O device (FDD, HDD, 

CD-ROM…….) from motherboard 

except LCD or monitor. 

Display 

OK? 

No 

Yes 

Replace monitor 

or LCD. 

Correct it. 

1. Replace faulty part. 

2. Connect the I/O device to the M/B 

one at a time to find out which part 

is causing the problem. 

Board-level 


Replace 

Motherboard 

System 

BIOS writes 

error code to port 

378H? 

No 

Check system clock and 

reset circuit. 

To be continued 

Clock and reset checking 

Yes 

Refer to port 378H 

error code description 

section to find out 

which part is causing 

the problem. 

109


+3V 

L517 

L513 

L14 

L9 

PCICLK_CARD 

PCICLK_LAN 

115 

P18 U17 

PCMCIA 

Controller 

R541 8.2K 

R81 10K 

120Z/100M 

120Z/100M 

120Z/100M 

120Z/100M 

FS2 FS1 FS0 CPU 3V66[5:0] PCI 

x 0 0 166.66 66.66 33.33 

001 

x 0 1 100.00 66.66 33.33 

x 1 0 200.00 66.66 33.33 

x 1 1 133.33 66.66 33.33 

Mid 0 0 Tristate Tristate Tristate 

Mid 0 1 TCLK/2 TCLK/2 TCLK/2 

Mid 1 0 Reserved Reserved Reserved 

Mid 1 1 Reserved Reserved Reserved 

0 : 0V 

1 : 3.3V 

J502 

P16 U15 

P17 

LAN Controller 

MiniPCI 

Connector 

UNIT : MHz 

PCICLK_MINIPCI 

VTT_PWRGD# 

+3VCLKCPU 

+3VCLKPCI 

+3VCLKANA 

+3VCLK66 

R117 

33 

R119 

33 

+3V 

C129 

33P 

C132 

33P 

R173 

4.7K 

R158 

4.7K 

R542 

33 

4 

3 

2 

1 


****** System Clock Check ****** 

FS0 

FS1 

FS2 

R114 

4.7K 

43 

28 

46,50 

8,14 

1,26,37 

19,32 

54 

55 

40 

13 

16 

12 

3 

X2 

14.318MHz 

2 

MULTSEL0 

P4 

U4 

Clock 

Generator 

PLL207-151 

45 

44 

49 

48 

21 

39 

29 

30 

39 

22 

7 

56 

11 

38 

10 

SMBDATA 

SMBCLK 

R121 33 

R116 33 

R138 33 

R130 33 

R109 33 

R112 33 

R663 

10K 

R111 33 

R108 33 

R139 33 

R159 33 

R127 33 

R107 33 

R131 33 

HCLK_MCH 

HCLK_MCH# 

66M_MCH 

48M_DREFCLK 

R662 

10K 

G 

S D 

G Q515 

2N7002 

S D 

Q516 

2N7002 

+3V 

P5 

P6 

HCLK_CPU 

HCLK_CPU# 

U502 

Memory 

Controller 

Montara-GM 

R31 

2.2K 

USBCLK_ICH 

66M_ICH 

PCICLK_ICH 

14M_ICH 

CLK_DDR[0:5] 

CLK_DDR[0:5]# 

SMBCLK 

SMBDATA 

PCICLK_LPC 8 

48M_SUPERIO 

20 

PCICLK_1394 

VDD3 

R44 

2.2K 

SMB_DATA 

SMB_CLK 

93 

P4 

U501 

CPU 

Pentium-M 

U510 

Super I/O 

P19 

J513, J514 

DDR SO-DIMM 

P9 P10 

U3 

I/O 

Controller 

Hub 

ICH4-M 

P15 U9 

1394 

Controller 

110

P11 


Primary EIDE Connector 

P11 

+3V_P 

VDD5 

U22 

D25 

MAX809 

3 

P20 

U504 

J4 

J509 

VCC 

Micro 

Controller 

H8/F3437 

C_RSTDRV2# 

Secondary EIDE Connector 

2 

P20 

RESET# 

1 

14 

49 

R15 

10K 

2 

C_RSTDRV1# 

R57 

0 

Q11 

MMBT3904L 

R77 

100K 

H8_RESET# 

H8_PWRON 

H8_PWRON_SB 

R252 

22 

R196 

22 

1 

2 

R237 

20K 

BAW56 

VDD5 

RP44 

0*8 

RP8 

0*8 

R7 

10K 

R238 

1K 

R58 

1K 

3 

+5V 

+5V 

R43 

10K 

R356 

10K 


****** Power Good & Reset Circuit Check ****** 

PWROK 

RSMPWRON 

+3V 

Q7 

DTC144TKA 

+3V 

Q13 

DTC144TKA 

R74 

100K 

VDD3 

Q19 

DTC144TKA 

+3V 

+3V 

R80 

10K 

R357 

10K 

U12 

MAX809 

RESET# VCC 3 

2 

P20 

VDD3 

VDD3 

R607 

10K 

3 

3 

R242 

4.7K 

Q5 

DTA144WK 

D26 

BAW56 

1 

2 

D29 

BAW56 

1 

2 

+3V 

PWROK 

RSMRST# 

ICH_PWRBTN# 

IDERST# 

SIDERST# 

P5 

U502 

Memory 

Controller 

Montara-GM 

P9 

U3 

I/O 

Controller 

Hub 

82801DBM 

ICH4-M 

PCIRST# 

ACRST# 

HCPURST# 

MCH_PCIRST# 

+3V 

14 

4,5 6 

7 

+3V 

14 

9,10 8 

7 

+3V 

14 

1,2 3 

7 

U2B 

74AHC08_V 

U2C 

74AHC08_V 

U2A 

74AHC08_V 

+VCCP 

R56 

51 

JL8 

JL10 

JL13 

JL12 

JL11 

JL5 

11 

P3 U501 

CPU 

Pentium-M 

LAN_PCIRST# 

P16 

114 U15 

TV_PCIRST# 

MINIPCI_PCIRST# 

1394_PCIRST# 

JL7 CB_PCIRST# 

LPC_PCIRST# 

13 

26 

92 

9 

LAN Controller 

P8 

U7 

TV Controller 

P17 

J520 

MINIPCI 

P15 

U9 

1394 Controller 

P18 

U17 

PC CardBus 

P19 

U510 

Super I/O 

P12 

U509 

Audio Codec 

STAC9750 

111



There is no display or picture abnormal on LCD although power-on-self-test is passed. 

VGA Controller Failure 

LCD No Display 

1. Confirm LCD panel or monitor is good 

and check the cable are connected 

properly. 

2. Try another known good monitor or 

LCD module. 

Display 

OK? 

No 

Remove all the I/O device & cable from 

motherboard except LCD panel or 

extended monitor. 

Display 

OK? 

No 

Yes 

Yes 

Replace faulty 

LCD or monitor. 

Connect the I/O device & cable to 

the M/B one at a time to find out 

which part is causing the problem. 

Board-level 


Replace 

Motherboard 

No 

Yes 

Re-soldering. 

One of the following parts on the mother-board may be 

defective, use an oscilloscope to check the following signal or 

replace the parts one at a time and test after each replacement. 


U502 

U3 

U504 

J504,J505 

D2,Q6 

F1,Q4,L5 

U2,JL9 

Q8,Q9 

L1~L4 

Check if 

U502, J505 are cold 

solder? 

+3V 

LCDVCC 

FPVDD 

LCD_ID[0:2] 

TXOUT[0:5]+ 

TXOUT[0:5]- 

TXCLKOUT[0,1]+ 

TXCLKOUT[0,1]- 

ENBL 

PCIRST# 

LID# 

ENABLE_BKLT 

112



P5 

U502 

Memory 

Controller 

Hub 

Montara-GM 

P9 P10 

U3 

I/O Controller 

ICH4-M 

There is no display or picture abnormal on LCD although power-on-self-test is passed. 

TXOUT[0:5]+ 

TXOUT]0:5]- 



FPVCC 

PCIRST#1 

+3V 

14 

PCIRST# 4,5 

U2B 

74AHC08_V 

6 

7 

R6 

10K 

+3V 

JL9 

C5 

0.1µ 

PCIRST#1 

+3V 

Q6 

DTC144TKA 

F1 

mircoSMDC110 

DVMAIN 

8 

7 

6 

5 

D 

R5 

470K 

Q4 

SI4800DY 

ENBL LID# 

LCD_ID[0:2] 

D2 

BAW56 

2 3 

1 

SW2 

RP6 

2.7K*4 

+3V 

+3V 

Q9 

DTC144TKA 

2 

1 

3 

Q8 

BAW56 

R48 

10K 

+5V 

G 

LID# 

S 

3 

2 

1 

24 

45 

C690 

0.1µ 

ENABLE_BKLT 

BLADJ 

P20 

U504 

H8/F3437 

C11 

10µ 

+5V 

VDD5S 

C12 

0.1µ 

L1 

L4 

L3 

L2 

C13 

1000P 

SW2 

L5 

120Z/100M 

Transfer 

Board 

120Z/100M 

120Z/100M 

120Z/100M 

120Z/100M 

C6 

0.1µ 

C7 

1000P 

LCDVCC 

C4 

0.1µ 

1,2 

J505 

P14 

Inverter 

Board 

2,3 

11 

1 

4 

5,6 

LCD Connector 

J504 

P21 

Inverter 

LCD 

113



There is no display or picture abnormal on CRT monitor, but it is OK for LCD. 

External Monitor No Display 

1. Confirm monitor is good and check 

the cable are connected properly. 

2. Try another known good monitor. 

Display 

OK? 

No 

Remove all the I/O device & cable 

from motherboard except monitor. 

Display 

OK? 

No 

Yes 

Yes 

Replace faulty monitor. 

Connect the I/O device & cable to 

the M/B one at a time to find out 

which part is causing the problem. 

Board-level 


Replace 

Motherboard 

No 

Yes 

Re-soldering. 

One of the following parts on the mother-board may be 

defective, use an oscilloscope to check the following signal or 

replace the parts one at a time and test after each replacement. 

Parts: 

Check if 

U502, J507 

are cold solder? 

U5 

U3 

J507 

F2 

D4 

L8 

Q501~Q505 

L503~L508 

Q3 

Q515 

Q516 

Signals: 

+5V 

CRT_DDA 

CRT_HSYNC 

CRT_VSYNC 

CRT_DDCK 

CRT_R 

CRT_G 

CRG_B 

SMB_DATA 

SMB_CLK 

CRT_IN 

114


P5 

U502 

Memory 

Controller 

Hub 

Montara-GM 

P9 P10 

U3 


ICH4-M 


There is no display or picture abnormal on CRT monitor, but it is OK for LCD. 

CRT_DDDA 

CRT_HSYNC 

CRT_ VSYNC 

CRT_ DDCK 

CRT_ R 

CRT_ G 

CRT_B 

SMB_DATA 

SMB_CLK 

CRT_IN 

R533 

2.2K 

+3V +3V 

+5V 

R508 

2.2K 

L505 120Z/100M 

L504 120Z/100M 

L503 120Z/100M 

R44 

2.2K 

VDD3 

R31 

2.2K 

CP501 

22P*4 

R527 

1K 

G 

S D 

Q502 

2N7002 

4 

3 

2 

1 

5 

6 

7 

G 

S D 

8X 

X 

Q505 

2N7002 

+3V 

G 

D S 

Q515 

2N7002 

D 

G 

Q516 

2N7002 

S 

G 

S D 

Q503 

2N7002 

4 

3 

2 

1 

5 

6 

7 

R663 

10K 

G 

S D 

8X 

X 

Q504 

2N7002 

CP502 

22P*4 

R662 

10K 

R511 

75 

+5V 

SMBDATA 

SMBCLK 

F2 

mircoSMDC110 

L506 120Z/100M 

L507 120Z/100M 

L509 120Z/100M 

L508 120Z/100M 

R510 

75 

R509 

75 

D4 

D1FS4 

+5V 

G 

D S 

Q501 

2N7002 

CP503 

22P*4 

D 

DDC2B 

5 

6 

7 

8 

4 

3 

2 

1 

G 

Q3 

2N7002 

S 

L8 

120Z/100M 

VGA_DDC2B 

VGA_DDDA 

VGA_HSYNC 

VGA_ VSYNC 

VGA_ DDCK 

VGA_ RED 

VGA_ GREEN 

VGA_BLUE 

JL502 

JL501 

9 

12 

13 

14 

15 

1 

2 

3 

16,17 

4 

11 

5 

J507 

P14 

External VGA Connector 

115


Extend DDRAM is failure or system hangs up. 

Memory Test Error 

1.If your system installed with expansion 

SO-DIMM module then check them for 

proper installation. 

2.Make sure that your SO-DIMM sockets 

are OK. 

3.Then try another known good SO-DIMM 

modules. 

Test 

OK? 

No 

Yes 

If your system host bus clock running at 

266MHZ then make sure that SO-DIMM 

module meet require of PC 266. 

Test 

OK? 

No 

Yes 



DDRAM module. 


DDRAM module. 

Board-level 


Replace 

Motherboard 

One of the following components or signals on the motherboard 

may be defective ,Use an oscilloscope to check the signals or 

replace the parts one at A time and test after each replacement. 

Parts: 

RP11 

RP13 

RP15 

RP17 

RP20 

RP22 

RP25 

RP28 

RP31 

RP33 

RP34 

RP37 

PR40 

R216 

R225 

Q515 

Q516 

R138 

R130 

R108 

U502 

U3 

U4 

J513 

J514 

Signals: 

+1.25V_DDR 

+2.5V_DDR 

CKE [0:3], 

CS# [0:3] 

SMA [1,2,4,5] 

SMAB [1,2,4,5] 

NB_MA [0,3,6:12] 

NB_MD [0:63] 

NB_DQS [0:7], 

NB_BA [0,1] 

NB_CB [0:7], 

NB_DM [0:8] 

NB_RAS# 

NB_CAS# 

NB_WE# 

SMB_DATA 

SMB_CLK 

HCLK_MCH 

HCLK_MCH# 

66M_MCH 

CLK_DDR [0:5] 

CLK_DDR [0:5]# 

116

P6 

U502 

Memory 

Controller 

Hub 

Montara-GM 


Extend DDRAM is failure or system hangs up. 

CKE [0:3], CS# [0:3], SMA [1,2,4,5], SMAB [1,2,4,5] 

NB_MA [0,3,6:12] 

NB_MD [0:63] 

NB_DQS [0:7], NB_BA [0,1] 

NB_CB [0:7], NB_DM [0:8] 

NB_RAS#, NB_CAS#, NB_WE# 

P9 

U3 


ICH4-M 

HCLK_MCH 

HCLK_MCH# 

66M_MCH 

SMB_DATA 

SMB_CLK 

R138 

33 

R130 

33 

R108 

33 

CLK_DDR [0:5] , CLK_DDR [0:5]# 

RP11,RP13,RP15,RP17,RP20 


RP34,RP37,RP40 10*8 

R216,R225 10 

VDD3 

R44 

2.2K 

49 

48 

22 

R31 

2.2K 

P4 


U4 

+3V 

G 

Clock 

Generator 

PLL207-151 

MA [0,3,6:12] 

MD [0:63] 

D S 

Q515 G 

2N7002 

D S 

Q516 

2N7002 

DQS [0:7], BA [0,1] 

MCB [0:7], DM [0:8] 

RAS#, CAS#, WE# 

R663 

10K 

29 

30 

+1.25V_DDR 

R662 

10K 

SMBDATA 

SMBCLK 

RP14,RP16~RP19,RP21,RP23 


RP32 56*8 

R194,R200,R221,R231,R215 

RR219,R226 56 

+2.5V_DDR 

R186 

75 

R185 

75 

C154 

0.01µ 

C150 

0.01µ 

CKE [0,1], CS# [0,1], SMA[1,2,4,5] 

CLK_DDR [0:2] , CLK_DDR [0:2]# 

C153 

0.1µ 

C149 

0.1µ 

+DDR_VREF 

C152 

0.1µ 

C151 

0.1µ 

CKE [2,3], CS[2,3]#, SMAB [1,2,4,5] 

CLK_DDR [3:5] , -CLK_DDR [3:5] 

J513 

P7 

DDR SODIMM 

J514 

P7 

DDR SODIMM 

117



Error message of keyboard or touch-pad failure is shown or any key does not work. 

Keyboard or Touch-Pad 

Test Error 

Is K/B or T/P 

cable connected to notebook 

properly? 

Try another known good Keyboard 

or Touch-pad. 

Test 

Ok? 

Yes 

No 

Yes 

No 

Correct it. 


Keyboard or Touch-Pad. 

Board-level 


Replace 

Motherboard 

Check 

U504, J1, J2 

for cold solder? 

No 

Yes 

Re-soldering. 

One of the following parts or signals on the motherboard 

may be defective, use an oscilloscope to check the signals 

or replace the parts one at a time and test after each 

replacement. 

Parts 

U510 

U504 

J1,J2 

SW3~SW8 

SW502~SW507 

F3 

L20 

L22,L23 

R227,R228 

R615 

X502 

Signals 

H8_VDDA 

SA2 

IRQ1 

IRQ12 

IOR# 

IOW# 

KI[0:7] 

KO[0:15] 

T_CLK 

T_DATA 

118

P19 

U510 

VDD[0:3] 

LPC 

Super I/O 

PC87393 



14,39,63,88 

C626 

0.1µ 

72 

73 

93 

87 

86 

83 

82 

Error message of keyboard or touch-pad failure is shown or any key does not work. 

C667 

0.1µ 

ROMCS# 

MCCS# 

VDD5 

C661 

0.1µ 

SA2 

IRQ1 

IRQ12 

IOR# 

IOW# 

+3V 

C647 

0.1µ 

L25 

120/100M 

+3V 

U503 

SN74CBTD3384 

8 

14 

Level 

Shift 

RP505 

4.7K 

9 

15 

C607 

0.1µ 

VDD5 

R605 

10K 

C611 

0.1µ 

RP503 

4.7K*8 

C269 

0.1µ 

H8_VDDA 

R603 

10K 

C603 

0.1µ 

H8_KBCS# 

H8_MCCS# 

9,59,4 

37 

95 

98 

93 

53 

54 

96 

97 

VCC[1,2,B] 

AVCC 

P20 

U504 

Micro 

Controller 

H8/F3437 

10 

57 

2 

3 

C610 

68P 

KI[0:7] 

KO[0:15] 

T_CLK 

T_DATA 

R615 

1M 

X502 

16MHZ 

KO0 

RP502 

47K*8 

VDD5 

SCRL_UP 

SW3,SW6 

KO0,1 SCRL_LEFT 

KI5 

KO1 

KO0,1 

SCRL_DN 

SCRL_RIGHT 

+5V 

L23 120Z/100MHZ 

L22 120Z/100MHZ 

C613 

68P 

SW_LEFT 

SW_RIGHT 

SW8 

SW7 

SW502~SW507 

SW4 

SW5 

F3 

0.5A/POLYSW 

CP1 

47P*4 

KI6 

KI7 

KI[0:2] 

L20 

120Z/100MHZ 

17~24 

1~16 

J1 

P20 

Internal 

Keyboard Connector 

R228 

0 

R227 

0 

C244 

0.1µ 

12 

1,2 

3,4 

5,6 

7,8 

J2 

P21 

Touch-Pad 

119

8.7 Hard Drive Test Error 

Hard Driver Test Error 


Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing 

data to hard disk. 

1. Check if BIOS setup is OK?. 

2. Try another working drive and cable. 

Re-boot 

OK? 

No 

Yes 

Check the system driver for proper 

installation. 

Re - Test 

OK? 

No 

Yes 

Replace the faulty parts. 

End 

Board-level 


Replace 

Motherboard 

One of the following parts or signals on the motherboard may 

be defective, use an oscilloscope to check the signals or replace 

the parts one at a time and test after each replacement. 


U3 

U23 

J4 

L24 

R349 

D19 

RP42 

RP43 

D26 

Q7 

RP44 

R252 

RP46 

+5V_HDD 

HDD_LED# 

PD_D[0:15] 

IDERST# 

PDCS1# 

PDA[0:2] 

PDDACK# 

PIORDY 

PDIOR# 

PDIOW# 

PDREQ 

PDCS3# 

IRQ14 

120

8.7 Hard Drive Test Error 

P10 

U3 

I/O 

Controller 

Hub 

82801DBM 

ICH4-M 

PD_D[0:15] 

PDCS1# 

PDA2 

PDDACK# 

PIORDY 

PDIOR# 

PDIOW# 

PDDREQ 

PDCS3# 


Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing 

data to hard disk. 

IDERST# 

PDA0 

PDA1 

IRQ14 

D26 

BAW56 

1 

2 

+5V 

3 

+3V 

R80 

10K 

L24 

120Z/100M 

+3V 

+3V 

Q7 

DTC144TKA 

R51 

8.2K 

C156 

1µ 

2~4 

+5V 

R43 

10K 

U23 

SI4788CY 

SOURCE[1:3] 

+3V 

DRAIN[1:3] 

R304 

4.7K 

5~7 

C167 

10µ 

+5V_HDD 

RP44 

0*8 

RP46 

0*4 

C183 

1µ 

+5V 

RP42,RP43 

0*8 

R252 

22 

R349 

330 

C338 

10µ 

D19 

CL-190G 

C_PD_D[0:15] 

C_RSTDRV1# 

C_PDCS1# 

C_PDA2 

C_PDDACK# 

C_PIORDY 

C_PDIOR# 

C_PDIOW# 

C_PDDREQ 

C_PDCS3# 

C_PDA0 

C_PDA1 

C_PINTRQ 

C341 

0.1µ 

HDD_LED# 

C339 

0.1µ 

40 

41, 42 

3~18 

2 

38 

35 

30 

28 

26 

24 

22 

37 

36 

34 

32 

J4 

P11 

Primary EIDE Connector for Hard-Disk 

121

8.8 CD-ROM Drive Test Error 


An error message is shown when reading data from CD-ROM drive. 

CD-ROM Driver 

Test Error 

1. Try another known good compact disk. 

2. Check install for correctly. 

Test 

OK? 

No 

Check the CD-ROM drive for 

proper installation. 

Re - Test 

OK? 

No 

Yes 

Yes 

Replace the faulty parts. 

End 

Board-level 


Replace 

Motherboard 

One of the following parts or signals on the motherboard may 

be defective, use an oscilloscope to check the signals or replace 

the parts one at a time and test after each replacement. 


U3 

U24 

J509 

D28 

L29 

R352 

D18 

D29 

Q13 

RP8~RP10 

R196 

RP3 

R366 

R375 

+5V_CDROM 

CD_LED# 

SIDE_OFF# 

SD_D]0:5] 

SIDERST# 

SDA[0:2] 

IRQ15 

SDDACK# 

SIORDY 

SDIOW# 

SDDREQ 

SDIOR# 

SDCS1# 

SDCS3# 

ICH_SIDE_IN# 

SIDEDET 

122

8.8 CD-ROM Drive Test Error 


An error message is shown when reading data from CD-ROM drive. 

P10 

U3 

I/O 

Controller 

Hub 

82801DBM 

ICH4-M 

SIDE_OFF# 

SD_D[0:15] 

SIDERST# 

SDA1 

IRQ15 

SDDACK# 

SIORDY 

SDIOW# 

SDDREQ 

SDIOR# 

SDA0 

SDCS1# 

SDCS3# 

SDA2 

ICH_SIDE_IN# 

SIDEDET 

D28 

BAW56 

1 

2 

D29 

BAW56 

1 

2 

3 

3 

+3V 

+3V 

R362 

10K 

R357 

10K 

+5V 

+3V 

Q13 

DTC144TKA 

L29 

120Z/100M 

+5V 

R356 

10K 

C255 

1µ 

2~4 

+3V 

R156 

8.2K 

U24 

SI4788CY 

SOURCE[1:3] 

VIN 

1 

+3V 

DRAIN[1:3] 

R50 

4.7K 

5~7 

RP8 

0*8 

RP3 

0*4 

+5V_CDROM 

C262 

10µ 

R366 470 

R375 5.6K 

C264 

1µ 

RP9,RP10 

0*8 

R196 

22 

R352 

330 

C115 

10µ 

D18 

CL-190G 

C125 

0.1µ 

C_SD_D[0:15] 

C_RSTDRV2# 

C_ SDA1 

C_ SINTRQ 

C_ SDDACK# 

C_ SIORDY 

C_ SDIOW# 

C_ SDDREQ 

C_ SDIOR# 

C_ SDA0 

C_ SDCS1# 

C_ SDCS3# 

C_ SDA2 

CD_LED# 

C124 

0.1µ 

J509 

P11 

Secondary EIDE Connector for CD-ROM 

123

8.9 USB Test Error 


An error occurs when a USB I/O device is installed. 

USB Test Error 

Check if the USB device is installed 

properly. (Including charge board.) 

Test 

OK? 

No 

Re-test 

OK? 

No 

Yes 

Replace another known good charge 

board or good USB device. 

Yes 

Correct it. 

Correct it. 

Board-level 


Replace 

Motherboard 

Check the following parts for cold solder or one of the following 

parts on the mother-board may be defective, use an oscilloscope 

to check the following signal or replace the parts one at a time 

and test after each replacement. 

Parts: 

U3 

U8 

J510 

J512 

J3 

J506 

L39 

L40 

F501 

L526 

L525 

Transfer Board 

U1 

L12 

Signals: 

+5V_P 

USBOC0# 

USBP[0:3]+ 

USBP [0:3] - 

USBOC3# 

USBOC1# 

124

8.9 USB Test Error 


An error occurs when a USB I/O device is installed. 

P10 

U3 

I/O 

Controller 

Hub 

82801DBM 

ICH4-M 

USBOC0# 

USBP0- 

USBP0+ 2 3 

3 

USBP1- 

USBP1+ 

USBOC3# 

USBP3- 

L39 

90Z/100M 

L40 

90Z/100M 

USBP3+ 3 4 

3 

USBOC1# 

USBP2- 

+5V_P 

+5V 

C187 

1µ 

3,4 

F501 

MINISMDC110 

P22 J506 J1 

8 

18 

7 

17 

U8 

RT9701-CBL 

VIN0,1 

P17 

VOUT0,1 

R616 

33K 

R617 

47K 

+5V_P 

USBOC1# 

USBP2- 

1,5 

C166 

1000P 

C111 

10µ 

JS1 

L526 

120Z/100M 

R204 

33K 

R205 

47K 

C679 

330µ 

C612 

1000P 

1 

4 

2 3 

L12 

90Z/100M 

USBP2+ 16 

15 USBP2+ 

1 4 

3 

C16 

1µ 

3,4 

U1 

RT9701-CBL 

VIN0,1 

VOUT0,1 

C14 

1000P 

1,5 

1 

2 

L525 

PLP3216S 

R13 

33K 

R12 

47K 

4 

1 

2 

+VCC_USB3 

C15 

150µ 

3 

2 

2 

3 

4 

2 

J510 

P17 

J512 

P17 

J3 

J510 

P22 


+VCC_USB 

1 

1 

1 

2 

+VCC_USB0 

+VCC_USB1 

J3 

USB Port 

125

8.10 Audio Failure 

Audio Failure 

1. Check if speaker cables are 

connected properly. 

2. Make sure all the drivers are 

installed properly. 

Test 

OK? 

Re-test 

OK? 

No 

1.Try another known good 

speaker, CD-ROM. 

2. Exchange another known 

good charger board. 

No 


No sound from speaker after audio driver is installed. 

Yes 

Yes 

Correct it. 

Correct it. 

Board-level 


Replace 

Motherboard 

Check the following parts for cold solder or one of the following parts on the 

motherboard may be defective,use an oscilloscope to check the following signal 

or replace parts one at a time and test after each replacement. 

1.If no sound cause 

of line out, check 

the following 

parts & signals: 

Parts: 

U3 

U509 

U511 

U18 

Q23 

Q26 

Q31 

L533 

L535 

L536 

L37 

L38 

Signals: 

AOUT_R 

AOUT_L 

DEVICE_DECT# 

SPDIFOUT 

DECT_HP#/OPT 

SPK_OFF 

2. If no sound cause 

of MIC, check 

the following 


Parts: 

U3 

U509 

J519 

L537 

L35 

Signals: 

H8_AVREF 

MIC 

3. If no sound cause 

of CD-ROM, check 

the following 


Parts: 

U3 

U509 

J509 

R309 

R302 

Signals: 

CDROM_LEFT 

CDROM_RIGHT 

126

U3 

I/O 

Controller 

Hub 

P18 

P10 

82801DBM 

ICH4-M 

U17 

PCMCIA 

Controller 

8.10 Audio Failure – Audio IN 

SPK_OFF 

SBSPKR 

CARDSPK# 



ACRST# 

ACSDIN0 

ACSYNC 

ACSDOUT 

ACBITCLK 

C620 

0.1µ 

+5V 

AGND 

R629 

47K 

C323 

0.1µ 

L31 

120Z/100M 

1 

2 

3 

To next page 

U508 

JS4 

NC7S32 

5 

4 

AGND 

L527 120Z/100M 

C315 

10µ 

+5V 

R633 

10K 

R632 

R631 

R634 

2K 

AGND 

C633 

0.1µ 

C621 

0.1µ 

AVDDAD 

22 

22 

AGND 

C644 

0.1µ 

PC_BEEP 

25,38 

11 

8 

10 

5 

6 

12 

AVDD[1,2] 

U509 

Audio Codec 

STAC9750 

PC_BEEP 

P12 

20 

18 

48 

35 

36 

C632 0.33µ 

C628 0.33µ 

SPDIFOUT 

AOUT_L 

AOUT_R 

H8_AVREF 

R328 

0 

C331 

4.7µ 

R340 

4.7K 

C665 

2.2µ 

AGND AGND 

21 MIC1 

C634 

1µ 

MIC 

R308 

6.8K 

To next page 

R301 

6.8K 

R654 

4.7K 

C666 

100P 

L537 

600Z/100M 

R309 6.8K 

R302 6.8K 

L35 

600Z/100M 

L13 

L32 

C340 

47P 

L538 

600Z/100M 

AGND 

AGND AGND CAGND 

CDROM_RIGHT 

CDROM_LEFT 

120Z/100M 

120Z/100M 

1 

2 

MIC1 

3 

5 

4 

2 

1 

AGND 

J519 

External 

MIC 

19 C631 0.33µ CDROM_COMM 3 

L36 120Z/100M 

L529 120Z/100M 

2 

1 

Internal 

MIC 

J509 

P11 

CDROM 

Connector 

127

AOUT_R 

C326 

4.7µ 

From previous page 

AOUT_L 

C318 

4.7µ 


8.10 Audio Failure – Audio OUT 

C327 

4.7µ 

C325 

0.1µ 

+5V 

CAGND 

C646 

0.1µ 

C324 

4.7µ 



L530 

120Z/100M 

JS5 

R645 

10K 

R646 

10K 

R649 

10K 

R648 

10K 

C629 

100µ 

C649 

0.1µ 

R650 

15K 

R651 

33K 

RHP_IN 

RLINE_IN 

LHP_IN 

C645 

0.1µ 

LLINE_IN 

R653 

33K 

R652 

15K 

21 

20 

7,18 

5 

4 

RLINE IN 

RHP IN 

LVDD/RVDD 

P13 

U511 

Amplifier 

APA2020A 

LHP IN 

LLINE IN 

ROUT+ 

LOUT+ 

SE/BTL# 

HP/LINE# 

14 

16 

22 

15 

3 

10 

C630 

100µ 

C664 

100µ 

LOUT+ 

LOUT- 

ROUT+ 

ROUT- 

AGND 

+5V 

AMP_SHUTDOWN 4 

Q23 

DTC144WK 

R324 

1K 

5 

AVDDAD 

R311 

15K 

C328 

100P 

L501 

600Z/100M 

L502 

600Z/100M 

U18 

NC7S32 

P22 

R330 

1K 

1 

2 

C329 

100P 

J503 

L 

1 

2 

J506 J1 

46 

48 

SPK_OFF 

AMP_DOWN 

+5V 

R327 

22 

R331 

22 

Q26 

DTC144TKA 

R347 

4.7K 

L37 

600Z/100M 

+5V 

R314 

4.7K 

R1 

SPDIFOUT 


Internal Speaker Connector 

45 

47 


L4 

600Z/100M 

L3 

600Z/100M 

1 

2 

DECT_HP#/OPT 

DEVICE_DECT# 

L533 

600Z/100M 

L535 600Z/100M 

L536 

600Z/100M 

J4 

R 

+3V 

R346 

10K 

Q513 

DTA144WK 

L38 

600Z/100M 

L531 

120Z/100M 

L532 

120Z/100M 

R1 Q31 

DTC144TKA 

5 

4 

3 

2 

1 

7 

8 

9 

R343 

10K 


Drive 

IC 

J518 

LED 

LINE OUT 

AVDDAD 

128


LAN Test Error 

1.Check if the driver is installed properly. 

2.Check if the notebook connect with the 

LAN properly. 

Test 

OK? 

An error occurs when a LAN device is installed. 

No 

Check if BIOS setup is ok. 

Re-test 

OK? 

No 

Yes 

Yes 

Correct it. 

Correct it. 


Board-level 


Replace 

Motherboard 



to check the following signal or replace the parts one at a time and 

test after each replacement. 


U3 

U15 

U17 

U16 

U11 

J515 

Q24 

Q20 

U2 

L26 

L27 

X4 

+LAN_A2.5V 

+LAN_D2.5V 

CARD_RI# 

PCICLK_LAN 

PCIRST# 

IN_PIRQE# 

PCI_REQ1 

PCI_FRAME# 

PCI_DEVSEL# 

PCI_TRDY# 

PCI_IRDY# 

PCI_PME# 

PCI_STOP# 

PCI_GNT1# 

PCI_PAR 

AD[0:31] 

CBE#]0:3] 

RXIN+ 

RXIN- 

TXD+ 

TXD- 

EECS 

EESK 

EEDI 

EEDO 

129

P18 

U17 

PCMCIA 

Controller 

CB710 

P9 

U3 

I/O 

Controller 

Hub 

82801DBM 

ICH4-M 


CARD_RI# 

An error occurs when a LAN device is installed. 

C316 

0.1µ 

+3V_P 

+3V 

14 

PCIRST# 4,5 

U2B 

6 

74AHC08_V 

7 

INT_PIRQE#, PCI_REQ1# 

PCI_FRAME#, PCI_DEVSEL# 

PCI_TRDY#, PCI_IRDY# 

PCI_PME#, PCI_STOP# 

PCI_GNT1#, PCI_PAR 

AD[0:31], CBE#[0:3] 

Q24 

DTC144WK 

Q20 

DTC144WK 

JL10 

LAN_WAKE 112 

PCICLK_LAN 

From U4 Clock Generator 

+3V 

+LAN_D2.5V 

R303 

2.2 

C311 

0.1µ 

LAN_PCIRST# 

RP1,RP2,RP4 

R150,R153 

8.2K*4 


43 

115 

114 

113,118 

15,19 

18,17 

119,21 

117,23 

VCCRAM 

WOL 

P16 

U15 

LAN 

Controller 

VT6105-LOM 

50 

58 

57 

54 

104 

105 

108 

109 

94 

95 

EECS 

EESK 

EEDI 

EEDO 

RXIN+ 

RXIN- 

TXD+ 

TXD- 

LANX1 

LANX2 

C284 

22P 

1 

2 

3 

4 

U16 

NM93C46 

CS 

SK 

DI 

DO 

+LAN_A2.5V 

R245 

49.9 

R246 

49.9 

3 

2 

4 

X4 

25MHZ 

P16 

1 

VCC 

GND 

L28 

120Z/100M 

R243 

49.9 

C279 

22P 

8 

5 

+3V_P 

C290 

1µ 

R244 

49.9 

L26 

PLP3216S 

2 

1 

3 4 

2 

L27 

PLP3216S 

+LAN_D2.5V +2.5V_DDR 

L33 

120Z/100M 

1 

3 4 

C273 

0.1µ 

1 

2 

7 

8 

3,6 

C298,C308 

0.1µ 

+2.5V_DDR +LAN_D2.5V 

+2.5V_DDR +LAN_A2.5V 

P16 

U11 

LF-H80P 

16 

15 

10 

9 

14 

11 

R229 

75 

R230 

75 

+LAN_A2.5V 

L34 

120Z/100M 

C286,C288,C296 0.1µ 

C287,C293 2.2µ 

PJRX+ 

PJRX- 

PJTX+ 

PJTX- 

C233 

1000P 

R222 

75 

R224 

75 

PJ7 

PJ4 

6 

P16 

3 

8 

7 

1,2 

4,5 

J515 

RJ45 LAN Connector 

130

PC Card & Card 

Reader Socket Failure 

1. Check if the PC Card or Card Reader 

device is installed properly. 

2. Confirm PC Card or Card Reader driver 

is installed ok. 

Test 

OK? 

No 

Try another known good PC 

Card or Card Reader device. 

Re-test 

OK? 

No 

Yes 

Yes 

Correct it 


8.12 PC Card & Card Reader Socket Failure 

An error occurs when a PC card or SD Card device is installed. 

Change the faulty 

part then end. 

Board-level 


Replace 

Motherboard 





Parts: 

U3 

U17 

U21 

J517 

J516 

U2 

Q22 

R270 

R279 

Signals 

PCICLK_CARD 

PCIRST# 

INT_PIRQF# 

PCI_REQ2# 

PCI_SERR# 

PCI_PERR# 

PCI_DEVSEL# 

PCI_FRAME# 

PCI_IRDY# 

PCI_TRDY# 

PCI_STOP# 

PCLKRUN# 

PCI_PME# 

PCI_GNT2# 

PIC_PAR 

SERIRQ 

SUSB# 

AD[0:31] 

CBE#[0:3] 

VCC5_EN# 

VCC3_EN# 

VPPD0 

VPPD1 

131

P9 

U3 

I/O 

Controller 

Hub 

82801DBM 

ICH4-M 

+3V 

14 

PCIRST# 1,2 

U2A 

3 

74AHC08_V 

7 

JL7 

CB_PCIRST# 


8.12 PC Card & SD Card Socket Failure 

An error occurs when a PC card or SD Card device is installed. 

INT_PIRQF# 

PCI_REQ2# 

PCI_SERR#, PCI_PERR#, PCI_DEVSEL# 

+SDVDD 

PCI_FRAME#, PCI_IRDY# 

PCI_TRDY#, PCI_STOP# 

PCLKRUN#, PCI_PME#, PCI_GNT2# 

PCI_PAR, SERIRQ, SUSB# 

AD[0:31], CBE#[0:3] 

R310 

0 

+3V +SDVDD 

Q22 

SI2301DS 

D S 

G 


+3V 

R292 

100K 

+3V 

PCICLK_CARD 

RP1,RP2 

RP4,R539 

8.2K*4 

SM_PWR3EN# 

SD_PWREN# 

MS_PWREN# 

P18 

U17 

PCMCIA 

CardBus 

& 

Card Reader 

Controller 

CB710 

VCC5_EN# 

VCC3_EN# 

VPPD0 

VPPD1 

+5V 

5,6 

2 

1 

15 

14 

C336 

0.1µ 

5VA,B 

VCCD0 

VCCD1 

VDDP0 

VDDP1 

P18 

U21 

TPS2211A 

OC 

SHDN 

3.3VA,B 

AVCCC,B,A 

AVPP 

+CARD_VCC 

8 

16 

3,4 

11-13 

10 

R332,R258 

43K 

CRST#, CAD11 

CAD[0:10,12:31], CCBE[0:3]# 

CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL# 

CPERR#, CSERR#, CPAR, CREQ#, CGNT#, CINT#, CCLK 

R2_D2, R2_D14, R2_A18, CCD[1,2]#, CVS[1,2], CBLOCK#, CAUDIO, CSTSCHG 

+SDVDD 

SDCD#, SD_WP# 

SD[0:3], SD_CMD 

SD_CLK1 

SM_CD#, SM_R/B, SM_WPD# 

SM_SD[0:7], SM_LVD, SM_WP#, SM_WE# 

SM_ALE, SM_RE#, SM_CLE, SM_CE# 

MS_BS, MS_SDIO 

MS_INS# 

MS_CLK1 

R287,R269,R290 

R271,R289 43K 

R270 10 

R279 10 

+3V 

R342 

10K 

R339 10K 

R268,R286 

43K 

C336 

0.1µ 

R272,R275 

R293 8.2K 

+3V 

+CARD_VCC 

C335 

2.2µ 

R295 

43K 

C297 

0.1µ 

+VPPOUT 

C337 

1µ 

SD_CLK 

MS_CLK 

C303 

0.1µ 

C306 

0.1µ 

J517 

P18 

Card Bus Socket 

J516 

P18 

Card Reader Socket 

132

8.13 IEEE 1394 Failure 

IEEE1394 Fail 

1. Check if the 1394 device is installed 

properly. 

2. Confirm 1394 driver is installed ok. 

Test 

OK? 


An error occurs when a IEEE 1394 device is installed. 

No 

Check if BIOS setup is ok. 

Re-test 

OK? 

No 

Yes 

Yes 

Correct it. 

Correct it. 

Board-level 


Replace 

Motherboard 





Parts: Signals 

U3 

U9 

U10 

J506 

U2 

JL11 

R220 

X3 


J1 

J5 

L5 

L6 

AD[0:31] 

CBE# [0:3] 

PCI_REQ0# 

PCI_FRAME# 

PCI_IRDY# 

PCI_TRDY# 

PCI_DEVSEL# 

PCI_STOP# 

INT_PIRQG# 

PCIRST# 

PCI_GNT0# 

PCI_PAR 

PCI_PERR# 

PCI_SERR# 

PCI_PME# 

PCICLK_1394 

EECS 

EECK 

EEDI 

EEDO 

TPA+ 

TPA- 

TPB+ 

TPB- 

TPBIAS1 

+3V 

1394_VCC 

1394_AVCC 

133

P9 

8.13 IEEE 1394 Failure 

+3V L19 

120Z/100M 

1394_AVCC 

C242 

0.1µ 

C219 

0.1µ 

+3V 

14 

PCIRST# 9,10 

U2C 

8 

74AHC08_V 

7 

C220 

0.1µ 

JL11 

C222 

0.1µ 


An error occurs when a IEEE 1394 device is installed. 

+3V L19 

120Z/100M 

1394_VCC 

U3 

I/O 

Controller 

Hub 

82801DBM 

ICH4-M 

C234 

0.1µ 

PCI_PAR, PCI_PME#, PCI_GNT0# 

PCI_REQ0#, INT_PIRQG# 

PCI_PERR#, PCI_DEVSEL# 

AD[0:31], CBE#[0:3] 

C241 

0.1µ 

29 

32 

C250 C249 C248 C224 

0.1µ 0.1µ 0.1µ 0.1µ 

31 

30 

+3V 

PCI_FRAME#, PCI_IRDY#, PCI_TRDY#, PCI_STOP# 

C230 

0.1µ 

PCICLK_1394 


C238 

0.1µ 

93 

1394_PCIRST# 92 

RP1,RP2 

R78,R132 

8.2K*4 

P15 

U9 

IEEE1394 

Controller 

VT6307L 

60 

61 

73 

72 

71 

70 

74 

C227 

10P 

EECS 

R220 1M 

TPA+ 

TPA- 

TPB+ 

TPB- 

EECK 

EEDI 

EEDO 

X3 

24.576MHZ 

TPBIAS 

R590 

54.9 

C597 

0.33µ 

C235 

10P 

R591 

54.9 

1 

2 

3 

4 

U10 

NM93C46 

R592 

54.9 

C598 

270P 

R593 

54.9 

R598 

4.99K 

P22 

8 

5 

J506 

26 

28 

32 

34 

+3V 

C252 

1µ 

J1 

25 

27 

31 

33 

TPA+ 

TPA- 

TPB+ 

TPB- 


1 

2 

4 3 

4 

L6 

L5 

3 

1 2 

4 

3 

2 

1 

J5 

1394 Socket 

134

9. Spare Parts List - 1 

Part Number Description Location(US) 

441999900215 AC ADPT ASSY OPTION;8080 

442672600031 AC ADPT ASSY;19V,3.16A,DELTA,706 

361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA 

361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W) 

541667530026 AK;EN,8080,UTILITY ONLY 

541667530013 AK;EU,BOX,8080 

441999900212 BATT ASSY OPTION;LI,8-CELL,8080 

441675300037 BATT ASSY,SANYO,8CELLS/4.0AH,808 

442675300002 BATT ASSY;14.8V/4.4AH,LI,4S2P,SA 

338536010052 BATTERY;LI,3.7V/2.2AH,18650,SANY 

242670800113 BFM-WORLD MARK;WINXP,7521N 

221675340001 BOX;AK,8080 

340675300015 BRACKET ASSY;TOUCHPAD,8080 

343675300001 BRACKET;HINGE,R,8080 

343675300004 BRACKET;IO,8080 

341675300004 BRACKET;LCD,QDI,L,8080 

341675300003 BRACKET;LCD,QDI,R,8080 

421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C 

421673400005 CABLE ASSY;TV-OUT,8640S 

272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT 

272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT C16,C3,C4,C5 

272075103702 CAP;.01U ,50V,+80-20%,0603,Y5V,S C121,C150,C154,C160,C175,C179 

272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S PC106,PC24,PC4,PC503,PC504,P 

272072473401 CAP;.047U,16V ,10%,0603,X7R,SMT 

272072473401 CAP;.047U,16V ,10%,0603,X7R,SMT C678 



272072104702 CAP;.1U ,16V,+80-20%,0603,Y5V,S C149,C151,C152,C153,C185,C218 

272073104703 CAP;.1U ,25V,+80-20%,0603,X7R,S 

272073104501 CAP;.1U ,25V,+80-20%,0603,Y5V,S PC578,PC6 

272075104701 CAP;.1U ,50V,+80-20%,0603,Y5V,S C1,C100,C102,C106,C110,C113,C 

272075104701 CAP;.1U ,50V,+80-20%,0603,Y5V,S C1,C10,C11,C12,C13,C2,C3,C4,C5 

272075104703 CAP;.1U ,50V,+80-20%,0603,Y5V,S C10,C11,C14,C15 

272075104703 CAP;.1U ,50V,+80-20%,0603,Y5V,S C6,C8 

272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM PC26 

272005104502 CAP;.1U ,CR,50V,20%,0805,Z5U,SM PC544 

272005104402 CAP;.1U ,50V,+/-10%,0805,X7R,SMT C690,PC529,PC579 

272072224402 CAP;.22U ,10V ,10%,0603,X7R,SMT PC574 

272072334701 CAP;.33U ,CR,16V ,+80-20%,0603,Y 

272072334701 CAP;.33U ,CR,16V ,+80-20%,0603,Y C597,C628,C631,C632 

272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S C12 

272072474701 CAP;.47U ,16V,+80-20%,0603,Y5V,S C17,C9 

272002474401 CAP;.47U ,CR,16V ,10%,0805,X7R,S C1,C2 

272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT C233 

272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT C19,C20 

272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C13,C166,C612,C642,C653,C7,PC 

272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C14 

627207510241 CAP;1000P,50V ,10%,0603,X7R,SMT C7 

272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM PC102,PC104,PC105,PC17,PC44,P 

272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S C517,C666 

272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C328,C329,C530,C536,C562,PC10 

272991107502 CAP;100u,6.3V,20%,18m,SMT,MASTUS C679 

135



272991107502 CAP;100u,6.3V,20%,18m,SMT,MASTUS C15 

272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SM C227,C235,C299,C302 

272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C11,C111,C115,C127,C134,C144,C 

272023106502 CAP;10U,25V,M,1210,T2.5MM,X5R,SM PC510,PC511,PC512,PC519,PC52 

272075152401 CAP;1500P,CR,50V,10%,0603,X7R,SM PC108,PC550 

272073151301 CAP;150P ,CR,25V,5% ,0603,NPO,SM PC15 

272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 PC539,PC540,PC70,PC71,PC76,P 

272433156502 CAP;15U ,TQC,25V,20%,H=1.9 ,7343 PC46,PC48,PC508,PC509,PC59,P 

272075181301 CAP;180P ,50V ,5% ,0603,NPO,SMT PC54 

272073180401 CAP;18P ,CR,25V ,10%,0603,NPO,S C36,C40 

272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT PC11,PC575 

272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C156,C157,C168,C183,C187,C190 

272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C16,C21,C22 

272002105403 CAP;1U ,CR,16V,10%,0805,X7R,SM 

272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC16 

272002105701 CAP;1U ,CR,16V ,-20+80%,0805,Y5 PC21 

272001225401 CAP;2.2U ,CR,10V ,10%,0805,X7R,S 

272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C135,C139,C141,C312,C346,C542 

272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C108,C14,C287,C293,C335 

272075200302 CAP;20P ,CR,50V ,5% ,0603,NPO,S C572,C581 

272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C10 

272075221401 CAP;220P ,CR,50V ,10%,0603,X7R,S C91 

272431227504 CAP;220U ,4V ,20%,7343,POSCAP,SM PC565,PC67 

272431227528 CAP;220U,2.5V,TPE-MC,20%,POSCAP, PC28,PC29,PC31,PC32,PC515,PC 

272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S 



272075220301 CAP;22P ,50V ,5% ,0603,COG,SMT C279,C284 

272011226701 CAP;22U ,CR,10V,1206,Y5V,+80~20% C131,C155,C540,C545,C559,C590 

272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C114,C118,C126,C598 

272075209001 CAP;2P ,CR,50V ,+-0.25PF,0603, 

272431337510 CAP;330U,2.5V,20%,POSCAP,H1.8,73 PC33,PC45,PC548,PC567 

272075330302 CAP;33P ,50V,5% ,0603,NPO,SMT C129,C132 

272075330401 CAP;33P ,CR,50V ,10%,0603,X7R,S C529,C543,C548 

272002475701 CAP;4.7U ,CR,10V ,+80-20%,0805,S PC100,PC82,PC99 

272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C331,C332,C591,C692 

272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C18 

272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y C318,C324,C326,C327,C616 

272012475502 CAP;4.7U ,CR,16V,20%,1206,Y5U,SM 

272013475701 CAP;4.7U ,CR,25V ,+80-20%,1206,Y C13 

272075472701 CAP;4700P,50V ,+ -20%,0603,X7R,S PC527 

272072471301 CAP;470P ,CR,16V ,5% ,0603,NPO,P 

272075470401 CAP;47P ,50V ,10%,0603,COG,SMT C340,C601,PC577 

272431476502 CAP;47U ,6.3V,20%,SP-CAP,7343,S 

272030680402 CAP;68P ,3KV,5%,1808,NPO,SMT,PR 

272075680302 CAP;68P ,50V ,5% ,0603,NPO,SMT C610,C613 

221675350012 CARD BOARD;FRAME,PALLET,W/CARRYI 

221675350011 CARD BOARD;TOP/BTM,PALLET,W/CARR 

221600020252 CARTON;BATTERY,CAIMAN,PWR 

221675320008 CARTON;NON-BRAND,W/CARRYING BAG, 

431675300001 CASE KIT;8080 

335152000044 CFM-BAT;FUSE THERMAL 98'C 

136



310111103007 CFM-BAT;THERMISTOR,10K,1%DISK,50 

273000111002 CHOKE COIL;120OHM/100MHZ,20%,321 L26,L27,L525 

273000111002 CHOKE COIL;120OHM/100MHZ,20%,321 L5,L6 

273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 L39,L40 

273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 L12 

361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P 

331000008038 CON;BAT,8P,2.5MM,SUYIN J501 

291000001001 CON;BATTERY,10P,FM,2MM,R/A,SMT 

331000007015 CON;BATTERY,FM,7P,R/A,8175,PRC 

331720015023 CON;D,FM,15P,2.29,R/A,3 ROW,TITA J507 

291000622007 CON;DIMM,R/A,200P,.6,H9.2,REVERS J513 

291000151201 CON;FPC/FFC,12P,0.5MM,R/A,SMT J2 

291000153011 CON;FPC/FFC,15P*2,.8MM,BD/BD,C10 J2 

291000152603 CON;FPC/FFC,26P,1MM,R/A,KBD,SMT J1 

331040050017 CON;HDR,FM,25P*2,R/A,C14301-1500 J501 

291000015201 CON;HDR,FM,26P*2,.5MM,ST,SMT J509 

291000015202 CON;HDR,FM,26P*2,1.0MM,ST,SMT,HR J1 

291000021101 CON;HDR,MA,11P*1,1.25,R/A,DF13-1 

291000011101 CON;HDR,MA,11P*1,1.25,ST,SMT J504 

291000013011 CON;HDR,MA,15P*2,1.0MM,H4.75,ST, J505 

291000024419 CON;HDR,MA,22P*2,2MM,H2.35,R/A,C J4 

291000015031 CON;HDR,MA,25P*2,0.3,ST,SMT,K071 J506 

291000015031 CON;HDR,MA,25P*2,0.3,ST,SMT,K071 J1 

291000020206 CON;HDR,MA,2P*1,1.25MM,H2.57,R/A J503 

291000020206 CON;HDR,MA,2P*1,1.25MM,H2.57,R/A J6 



291000010209 CON;HDR,MA,2P*1,1.25MM,H4.2,ST,S J511 

291000010209 CON;HDR,MA,2P*1,1.25MM,H4.2,ST,S J4 

291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM J2 

291000010503 CON;HDR,R/A,5P,.5,87152-0507,ACE J3 

331000004009 CON;IEEE1394,MA,4P*1,0.8MM,R/A J5 

291000253702 CON;MEMORY CARD,37P,SD,SM,SSFDC, J516 

331870007007 CON;MINI DIN,7P,R/A,W/GROUND,330 J508 

291000616801 CON;PCMCIA CARD,68P,TAI-SOL,WEAS J517 

331810006044 CON;PHONE JACK,6P2C,H11.5,RJ11,T J7 

291000810806 CON;PHONE JACK,8P8C,SMD,RJ45 J515 

331840010005 CON;POF MINI JACK,10P,W/SPDIF,2F J518 

331910003034 CON;POWER JACK,3P,D=2.5,SINGATRO PJ501 

331840005013 CON;STEREO JACK,5P,R/A,28MF60-07 J519 

331040008015 CON;USB,MA,R/A,4P*1,DIP,C10713,A J510,J512 

331040008015 CON;USB,MA,R/A,4P*1,DIP,C10713,A J3 

291000410301 CON;WFR,MA,3P,1.25,ST,SMT/MB J502 

346673800009 CONDUCTIVE TAPE;CONNECTOR,LCD,83 

342503200003 CONTACT PLATE;W4L18T0.15,7521/GR 

342502900001 CONTACT PLATE;W4L27T0.15,7068 

342503200005 CONTACT PLATE;W4L30T0.15,GRAMPUS 

342503200004 CONTACT PLATE;W4L63T0.15,1/4,T T 

342675300005 CONTACT PLATE;W5L27T0.13,8080,PW 

342675300007 CONTACT PLATE;W5L43.5T0.13,8080, 

342675300006 CONTACT PLATE;W5L45T0.13,8080,PW 

342503400002 CONTACT PLATE;W5L9T0.13,7170LI,P 

137



340675300006 COVER ASSY;8080 

340675300013 COVER ASSY;DIMM,8080 

340675300010 COVER ASSY;HDD,8080 

340675300008 COVER ASSY;LCD,8080 

344675300019 COVER;BATT,8080 

344675300012 COVER;CABLE,LCD,8080 

344675300027 COVER;HEATSINK,8080 

344675300011 COVER;HINGE,L,8080 

344675300010 COVER;HINGE,R,8080 

272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S CP501,CP502,CP503 

272625470401 CP;47P*4 ,8P,50V ,10%,1206,NPO,S CP1 

331660020005 DIMM SOCKET;DDR SODIMM 200P, CA0 J514 

288100140007 DIODE;B140,40V,1A,SMA,DIODES,SMT PD12,PD508,PD510,PD511 

288100340008 DIODE;B340LA,40V,3A,SMA,DIODES,S PD503,PD504,PD506,PD507 

288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D27,PD10,PD11,PD505 

288100054001 DIODE;BAT54,30V,200mA,SOT-23 D501,D502 

288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D503,D9,PD4,PD7 

288100099001 DIODE;BAV99,70V,450MA,SOT-23 

288100099001 DIODE;BAV99,70V,450MA,SOT-23 PD501,PD502 

288100056003 DIODE;BAW56,70V,215mA,SOT-23 D2,D25,D26,D28,D29,D3,PD509,P 

288100084002 DIODE;BZX84C5V6,5.2~6V,350mA,SOT ZD3,ZD4 

288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP, D4 

288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D30 

288100020001 DIODE;RLZ20C,ZENER,19.23V,5%,SMT PD1 

288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD2 



288100056001 DIODE;RLZ5.6B,ZENER,5.6V,5%,LL34 D1,D504 

288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER PD5 

288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM ZD5 

288100018003 DIODE;UDZS18B,ZENER,18V,SOD-323, ZD1,ZD2 

344675300034 DUMMY CARD;PCMCIA,8080 

272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S C629,C630,C664 

227675300006 END CAP;W/CARRYING BAG,8080 

481675300002 F/W ASSY;KBD CTRL,8080 U504 

481675300001 F/W ASSY;SYS/VGA BIOS,8080 U19 

273000150002 FERRIET CHIP;120OHM/100MHZ,2012, L14,L19,L20,L21,L33,L34,L513,L 

273000610008 FERRITE ARRAY;120OHM/100MHZ,TKIN FA1 

273000130001 FERRITE CHIP;120OHM/100MHZ,1608, L15,L17,L2,L22,L23,L25,L28,L3, 

273000130001 FERRITE CHIP;120OHM/100MHZ,1608, L1,L7,L8 

273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L1,L24,L29,L31,L4,L5,L8,PL1,PL 

273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L10,L11 

273000150001 FERRITE CHIP;220OHM/100MHZ,2012, L1 

273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1 L35,L37,L38,L501,L502,L536,L53 

273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1 L3,L4 

421467530001 FFC;TOUCHPAD,8080 

342600002059 FINGER;EMI GROUNDING SMD FINGER TP18,TP19,TP21,TP22,TP23 

342600002062 FINGER;EMI GROUNDING SMD FINGER, TP1,TP12,TP14,TP16,TP2,TP3,T 

288001001001 FIR,GP2W1001YP,GDE VIEW,10P,SMT, U2 

245600010007 FLOW CARD;M/B,WHITE 

245600010016 FLOW CARD;SPS,GRAY 

295000010028 FUSE;0.14A/60V,POLY SWITCH,PTC,S F1 

138



295000010048 FUSE;0.5A/15V,POLY SWITCH,SMD F3 

295000010014 FUSE;1.1A/6V,POLY SWITCH,PTC,SMD F1,F2,F501 

295000010105 FUSE;1A,NORMAL,1206,SMT F502,PF501 

295000010114 FUSE;FAST,1.75A,63VDC,1206,SMT,P 

335152000062 FUSE;LR4-730,POLY SWITCH,PRC 

295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF1,PF2 

345675300027 GASKET; AUDIO, 8080 

345675300028 GASKET; CARD_READ, M/B, 8080 

345675300029 GASKET; PCMCIA, M_b-1, 8080 

345675300030 GASKET; PCMCIA, M_b-2, 8080 

345675300008 GASKET;1394, TRANS-B,8080 

345675300010 GASKET;BRACKET, I/O,8080 

345675300011 GASKET;I/O,8080 

345675300012 GASKET;LANS,M-B,8080 

345675300007 GASKET;MODEM, TRANS-B,8080 

345675300014 GASKET;USB, TRANS-B,8080 

345675300013 GASKET;USB,M-B,8080 

230000010004 GLUE;9001B,BLACK,PRC 

230000010003 GULE;9001A,BLACK,PRC 

451675300091 HDD ME KIT;8080 

340675300003 HEATSINK ASSY;8080 

340675300012 HEATSINK ASSY;NORTH BRIDGE,8080 

340675300002 HINGE;LCD,L,8080 

340675300001 HINGE;LCD,R,8080 

344673550001 HOLDER;PCMCIA,TAI-SOL,WEASEL2 



340675300007 HOUSING ASSY;8080 

340675300009 HOUSING ASSY;LCD,8080 

451675300001 HOUSING KIT;8080 

344675300020 HOUSING;BATT,8080 

344675300032 HOUSING-ROM,8080 

291000616802 IC SOCKET;BANIAS m-FCBGA478P, TY U501 

282574008005 IC;74AHC08,QUAD 2-I/P AND,TSSOP, U2 

282574014004 IC;74AHC14,HEX INVERTER,TSSOP,14 U20 

282574373004 IC;74AHC373,OCT D-TRAN,TSSOP,20P U512 

282574132001 IC;74AHCT1G32,SINGLE OR GAT,SOT2 U18,U508 

282074338402 IC;74CBTD3384,10 BIT BUS SW,TSOP U503 

284501021003 IC;ADM1021A,TEMPERATURE MTR,SSOP U1 

286308800006 IC;AME8800AEEV,VOL REG.,SOT23-5, U516 

286301117021 IC;AMS1117,VOL REGULATOR,1A,SOT- U5,U6 

286300317010 IC;AMS3107C, VOLTAGE REGULATOR, U506 

286302020001 IC;APA2020ARI,AUDIO AMP,2W,TSSOP U511 

286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT U4 

286300710002 IC;CB710,CARDBUS/CARD READER,LFG U17 

284507011001 IC;CH7011A,TV ENCODER,LQFP,64P U7 

286302211002 IC;CP2211,POWER DISTRI SW,SSOP16 U21 

283466570001 IC;EEPROM,9346,64*16 BITS,SO8,SM U10,U16 

283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U3 

283480404002 IC;FLASH,512K*8-70,PLCC32,A29040 

284582801044 IC;FW82801DBM,ICH4-M,BGA,421P U3 

286300690003 IC;G690E,RESET CIRCUIT,4.38V,SOT U22 

139



284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P, 

286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU4 

286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF PU23,PU502 

286301907001 IC;MAX1907A,PWM CONTROLLER,40-QF PU505 

286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P PU3 

286300809009 IC;MAX809STR,RESET CIRCUIT,2.93V U12 

286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR U1 

284500000050 IC;MONTARA-GM GMCH,MICRO-FCBGA,7 U502 

286300965001 IC;OZ965R,CCFL CTRL,TSSOP16,O2 

284587393002 IC;PC87393F,TQFP,100P U510 

284520715001 IC;PLL207-151,CLOCK GEN,SSOP,56P U4 

286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U8 

286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U1 

286300812002 IC;S-812C,DECECTOR,SOT-89,PRC U2 

286301486001 IC;SC1486,PWM CTRL,SC,TSSOP-28 PU22 

286300338001 IC;SC338,FET CTRL,SC,MSOP-10 PU13 

286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ4 

282074164002 IC;SN74LV164APWR,SIPO REGISTER,T U513 

284509750002 IC;STAC9750T,AC97 CODEC,TQFP,48P U509 

286300594001 IC;TL594C,PWM CONTROL,SO,16P PU2 

284506105001 IC;VT6105LOM, PCI LAN CONTROLLER U15 

284506307001 IC;VT6307L,PCI-1394,2PORT,LQFP,1 U9 

273000990018 INDUCTOR;10uH,CDRH125,SUMIDA,SMT PL512,PL514 

273000990158 INDUCTOR;3.0UH,SPC-1205P,H6.0,TM PL508,PL510,PL515 

273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT PL502 



273000990159 INDUCTOR;4.7UH,SPC-1205P,H6.0,TM PL513 

273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI PL506 

346675300019 INSULATOR; CARD_READ, M_B, 8080 



346675300013 INSULATOR; HDD, CONN, M/B, 8080 

346675300012 INSULATOR; MB, 8080 

346503100005 INSULATOR;5,BATTERY ASSY,7521Li 

346503400502 INSULATOR;BATT ASSY,L22R9.2,8175 

346503200101 INSULATOR;BATT ASSY,POLY,W30L64, 

346503400503 INSULATOR;BATT ASSY,W7L13,8175 

346675300003 INSULATOR;DDR,M/B,8080 

346503400301 INSULATOR;FOR 3 CELLS,DOUBLE-FA, 

346669900004 INSULATOR;INVERTER,7170 

346675300020 INSULATOR;INVERTER_B,ESD,LCD,808 

346675300002 INSULATOR;MINIPCI,M/B,8080 

346503400203 INSULATOR;ONE ROUND,STINGRAY 

346675300010 INSULATOR;PCB ASSY,8080 

346675300004 INSULATOR;PCMCIA,M/B,8080 

346675300009 INSULATOR;TRANS-BD,8080 

451675300002 LABEL KIT;NON-BRAND,8080 

242600000145 LABEL;10*10,BLANK,COMMON 

242600000380 LABEL;10*8MM,BIOS,HI-TEMP 260 

242662300009 LABEL;25*10MM,3020F 

242662300009 LABEL;25*10MM,3020F 

140



242600000439 LABEL;25*6,HI-TEMP,COMMON 

242600000439 LABEL;25*6,HI-TEMP,COMMON 

242600000378 LABEL;27*7MM,HI-TEMP 260'C 

242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE 




242600000232 LABEL;6*6MM,GAL,BLANK,COMMON 

242675300001 LABEL;AGENCY-GLOBAL,8080 

242600000157 LABEL;BAR CODE & S/N,13.5*75,COM 

242675300002 LABEL;BATT 14.8V/4.4AH,LI,SANYO, 

242600000433 LABEL;BLANK,11*5MM,COMMON 

242669900009 LABEL;BLANK,60*80MM,7170 

242600000452 LABEL;BLANK,7MM*7MM,PRC 

242600000452 LABEL;BLANK,7MM*7MM,PRC 

242664800013 LABEL;CAUTION,INVERT BD,PITCHING 

242600000001 LABEL;PAL,20*5MM,COMMON 

242600000315 LABEL;RED ARROW HEAD,PRC 

242600000315 LABEL;RED ARROW HEAD,PRC 

242600000446 LABEL;S/N,INVERTER,20MM*3MM,PRC 

441675300001 LCD ASSY;TFT,QDI,14.1",XGA,W/O G 

451675310001 LCD ME KIT;TFT,QDI,XGA,14",8080 

413000020349 LCD;QD141X1LH12,TFT,XGA,14.1",QD 

294011200150 LED;BLUE,H0.55,LTST-C191TBKT,SMT D18,D19,D20,D21,D22,D23,D24 

294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190 



294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT D10,D11,D12,D13,D14,D15,D16,D 

294011200070 LED;RED/GREEN,19-22SRVGC/TR8,LED 

526267530024 LTXNX;8080/T4XX/XXX/3XX9/L1C3A/X 

561567530003 MANUAL KIT;EU,8080,N-B 

561567530021 MANUAL;USER'S,EN,8080,N-B 

561567530023 MANUAL;USER'S,EU,8080,N-B 

339115000030 MICROPHONE;-36dB+-3dB,D5.8*H3.4, MIC1 

291000251246 MINIPCI SOCKET;124P,R/A,0.8MM,H= J520 

242675300003 NAMEPLATE;COVER,8080 

416267530901 NB PF OPTION;XGA,14.1",8080 

416267530001 NB PF;QDI,14.1",XGA,W/O GPRS,808 

461675310002 PACKING KIT;14",NON-BRAND,BAG,80 

461675300003 PACKING KIT;8080 BATT,SANYO,8CEL 

227675300005 PAD;LCD/KB,ANIT-STATIC,8080 

224671830001 PALLET;1300*1100*126,GP2 

221675350002 PARTITION;AK BOX,8080 

221600050218 PARTITION;BATTERY,MARLIN,CAIMAN, 

221675350001 PARTITION;IN CARTON,8080 

221675350013 PARTITION;PALLET,W/CARRYING BAG, 

221600050219 PARTITION;TOP/BTM,BATTERY,MARLIN 

221675350009 PARTITION;W/CARRYING BAG,8080 

412672300001 PCB ASSY;FAX MODEM 56K,MDC56S-I, 

316675300002 PCB;PWA-8080/BATT GAUGE BD,SMT 

316675300003 PCB;PWA-8080/BATT PROTECTION BD, 

316675300005 PCB;PWA-8080/CD-ROM TRANS BD R00 

141



316675300001 PCB;PWA-8080/MOTHER BD R03 

316675300004 PCB;PWA-8080/TRANS BD R03 

316503400101 PCB;PWA-STINGRAY/INVERTER BD 

222600020049 PE BAG;50*70MM,W/SEAL,COMMON 

222600020310 PE BAG;70X100MM,W/SEAL,COMMON 

222670820003 PE BAG;L560*W345,7521N 

222670000001 PE BUBBLE BAG;BATTERY,7521 

222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS 

411675300013 PWA,PWA-8080/BATT BD,SANYO 

411675300014 PWA,PWA-8080/BATT GAUGE BD,SANYO 

411675300015 PWA,PWA-8080/BATT PROTECTION BD, 

411675300012 PWA;PWA-8080,CD-ROM,TRANSLATION 

411675300001 PWA;PWA-8080,MOTHER BD 

411675300003 PWA;PWA-8080,MOTHER BD,SMT 

411675300002 PWA;PWA-8080,MOTHER BD,T/U 

411675300005 PWA;PWA-8080,TRANSLATION BD,SMT 

411675300004 PWA;PWA-8080,TRANSLATION BD,T/U 

411503400201 PWA;PWA-STINGRAY/INVERTER BD 

411503400202 PWA;PWA-STINGRAY/INVERTER BD,SMT 

332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175 

271046017301 RES;.001,2W,5%,2512,CYNTEC,SMT PR35 

271046087301 RES;.008 ,2W,5% ,2512,SMT PR71 

271045107101 RES;.01 ,1W ,1% ,2512,SMT PR59,PR62,PR70 

271586026101 RES;.02 ,2W,1%,2512,SMT PR24,PR505 

271046257101 RES;.025 ,2W ,1% ,2512,SMT,PRC R18,R18A 



271002000301 RES;0 ,1/10W,5% ,0805,SMT L13,L32,L36,L529,L6,R202,R310, 

271002000301 RES;0 ,1/10W,5% ,0805,SMT R15 

271071000002 RES;0 ,1/16W,5% ,0603,SMT L527,PR103,PR104,PR34,PR38,PR 

271071000002 RES;0 ,1/16W,5% ,0603,SMT R10,R4 

271071127111 RES;1.27K,1/16W,1% ,0603,SMT R181 

271071152101 RES;1.5K ,1/16W,1% ,0603,SMT 

271071152101 RES;1.5K ,1/16W,1% ,0603,SMT R540 

271071196111 RES;1.96K,1/16W,1% ,0603,SMT PR105 

271071100302 RES;10 ,1/16W,5% ,0603,SMT 

271071100302 RES;10 ,1/16W,5% ,0603,SMT PR18,PR536,PR77,PR90,PR91,R1 

271071102211 RES;10.2K,1/16W,1% ,0603,SMT 

271071101101 RES;100 ,1/16W,1% ,0603,SMT R191,R208,R576,R582,R586 

271071101301 RES;100 ,1/16W,5% ,0603,SMT R248,R529 

271071101301 RES;100 ,1/16W,5% ,0603,SMT R6 

271071104101 RES;100K ,1/16W,1% ,0603,SMT 

271071104101 RES;100K ,1/16W,1% ,0603,SMT PR22,PR540,PR8 

271071104101 RES;100K ,1/16W,1% ,0603,SMT R14,R16,R23 

271071104101 RES;100K ,1/16W,1% ,0603,SMT R2,R7 

271071104302 RES;100K ,1/16W,5% ,0603,SMT PR13,PR14,PR15,PR39,PR507,PR 

271071104302 RES;100K ,1/16W,5% ,0603,SMT R19 

271071107311 RES;107K ,1/16W,1% ,0603,SMT PR83 

271071103701 RES;10K ,1/16W,.1%,0603,SMT PR10,PR7,R182 

271071103101 RES;10K ,1/16W,1% ,0603,SMT 

271071103101 RES;10K ,1/16W,1% ,0603,SMT PR21,PR25,PR55,PR56,PR63,PR7 

271071103302 RES;10K ,1/16W,5% ,0603,SMT PR537,R10,R110,R126,R135,R142 

142



271071103302 RES;10K ,1/16W,5% ,0603,SMT R20,R21 

271071106301 RES;10M ,1/16W,5% ,0603,SMT R52,R59 

271071131101 RES;130 ,1/16W,1% ,0603,SMT R83 

271071134701 RES;130K ,1/16W,0.1% ,0603,SMT PR5 

271071137011 RES;137 ,1/16W,1% ,0603,SMT R177 

271071141102 RES;140 ,1/16W,1% ,0603,SMT R584 

271071151101 RES;150 ,1/16W,1% ,0603,SMT R548,R571,R594,R597,R82,R91 

271071151302 RES;150 ,1/16W,5% ,0603,SMT R60 

271071154101 RES;150K ,1/16W,1% ,0603,SMT 

271071153101 RES;15K ,1/16W,1% ,0603,SMT 

271071153101 RES;15K ,1/16W,1% ,0603,SMT PR12 

271071153301 RES;15K ,1/16W,5% ,0603,SMT R311,R650,R652 

271071184301 RES;180K ,1/16W,5% ,0603,SMT R341,R515 

271071102102 RES;1K ,1/16W,1% ,0603,SMT 

271071102102 RES;1K ,1/16W,1% ,0603,SMT PR555,R507,R521,R87,R94 

271071102302 RES;1K ,1/16W,5% ,0603,SMT R210,R211,R218,R232,R238,R284 

271071102302 RES;1K ,1/16W,5% ,0603,SMT R6 

271071102302 RES;1K ,1/16W,5% ,0603,SMT R10,R24,R5,R8 

271071105101 RES;1M ,1/16W,1% ,0603,SMT 

271071105101 RES;1M ,1/16W,1% ,0603,SMT PR85 

271071105301 RES;1M ,1/16W,5% ,0603,SMT PR101,PR11,PR41,PR517,PR68,R 

271071105301 RES;1M ,1/16W,5% ,0603,SMT R11,R3,R9 

271071228301 RES;2.2 ,1/16W,5% ,0603,SMT R303 

271071222302 RES;2.2K ,1/16W,5% ,0603,SMT R235,R236,R31,R44,R508,R533,R7 

271071225301 RES;2.2M,1/16W,5% ,0603,SMT R1,R4 



271071249111 RES;2.49K,1/16W,1% ,0603,SMT PR26 

271071272101 RES;2.7K ,1/16W,1% ,0603,SMT PR538 

271071201301 RES;200 ,1/16W,5% ,0603,SMT PR32,PR36,R49 

271071201301 RES;200 ,1/16W,5% ,0603,SMT R15,R17 

271071203101 RES;20K ,1/16W,1% ,0603,SMT 

271071203101 RES;20K ,1/16W,1% ,0603,SMT PR503,PR526,PR57,PR64,PR73,P 

271071203302 RES;20K ,1/16W,5% ,0603,SMT R237 

271071220101 RES;22 ,1/16W,1% ,0603,SMT R128 


271071221302 RES;22 ,1/16W,5% ,0603,SMT R11,R7,R9 

271071232271 RES;23.2K,1/16W,.1%,0603,SMT PR6 

271071243011 RES;243 ,1/16W,1% ,0603,SMT R583 

271071249311 RES;249K ,1/16W,1% ,0603,SMT PR31 

271071261212 RES;26.1K,1/16W,1%,0603,SMT PR58 

271071274811 RES;27.4 ,1/16W,1% ,0603,SMT R25,R520,R549,R566,R573,R98 

271071283101 RES;28K ,1/16W,1% ,0603,SMT PR541 

271071294311 RES;294K ,1/16W,1% ,0603,SMT PR3 

271071202102 RES;2K ,1/16W,1% ,0603,SMT R178,R88 

271071202301 RES;2K ,1/16W,5% ,0603,SMT R634 

271071205101 RES;2M ,1/16W,1% ,0603,SMT 

271071332302 RES;3.3K ,1/16W,5% ,0603,SMT PR17 

271071301101 RES;300 ,1/16W,1% ,0603,SMT PR554 

271071301301 RES;300 ,1/16W,5% ,0603,SMT R22 

271071301011 RES;301 ,1/16W,1% ,0603,SMT R547,R572 

271071301311 RES;301K ,1/16W,1% ,0603,SMT PR1,PR534 

143

9. Spare Parts List – 10 


271071309311 RES;309K ,1/16W,1% ,0603,SMT R12 

271071324012 RES;324K ,1/16W,1% ,0603,SMT PR506 


271071331101 RES;330 ,1/16W,1% ,0603,SMT R580 


271071333301 RES;33K ,1/16W,5% ,0603,SMT PR19,PR508,R204,R616,R651,R65 

271071333301 RES;33K ,1/16W,5% ,0603,SMT R13 

271071390302 RES;39 ,1/16W,5% ,0603,SMT R65 

271071478301 RES;4.7 ,1/16W,5% ,0603,SMT PR4 

271013478301 RES;4.7 ,1/4W,5% ,1206,SMT R16,R18 

271071475112 RES;4.75K,1/16W,1% ,0603,SMT PR60,PR94 

271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR29,PR37 

271071472302 RES;4.7K ,1/16W,5% ,0603,SMT PR509,PR510,R114,R158,R173,R2 

271071472302 RES;4.7K ,1/16W,5% ,0603,SMT R3 

271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR504,R598 

271071402811 RES;40.2 ,1/16W,1% ,0603,SMT R556 

271071431102 RES;432 ,1/16W,1% ,0603,SMT PR539 

271071433301 RES;43K ,1/16W,5% ,0603,SMT R258,R268,R269,R271,R273,R274 

271071471101 RES;470 ,1/16W,1% ,0603,SMT 

271071471302 RES;470 ,1/16W,5% ,0603,SMT R323,R366,R376,R687 

271071471302 RES;470 ,1/16W,5% ,0603,SMT R13 

271071474301 RES;470K ,1/16W,5% ,0603,SMT PR30,PR74,PR95,R4,R5 

271071475011 RES;475 ,1/16W,1% ,0603,SMT R124 

271071473301 RES;47K ,1/16W,5% ,0603,SMT PR9,R205,R32,R361,R365,R379,R 

271071473301 RES;47K ,1/16W,5% ,0603,SMT R12 



271071487811 RES;48.7 ,1/16W,1% ,0603,SMT R89 

271071487211 RES;48.7K,1/16W,1% ,0603,SMT 

271071487011 RES;487 ,1/16W,1% ,0603,SMT,MUS R90 

271071499811 RES;49.9 ,1/16W,1% ,0603,SMT R115,R120,R125,R129,R137,R154 

271071499211 RES;49.9K,1/16W,1% ,0603,SMT PR535 

271002515302 RES;5.1M ,1/8W ,5% ,0805,SMT,PRC 

271071562111 RES;5.62K,1/16W,1% ,0603,SMT PR78 

271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R375 

271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R25 


271071549811 RES;54.9 ,1/16W,1% ,0603,SMT R24,R26,R27,R590,R591,R592,R59 


271071561101 RES;560 ,1/16W,1% ,0603,SMT 

271071604111 RES;6.04K,1/16W,1% ,0603,SMT R259 

271071619111 RES;6.19K,1/16W,1% ,0603,SMT PR28 

271071634111 RES;6.34K,1/16W,1% ,0603,SMT PR525,R599 

271071682301 RES;6.8K ,1/16W,5% ,0603,SMT R301,R302,R308,R309 

271071604811 RES;60.4 ,1/16W,1% ,0603,SMT R587,R588 

271071604112 RES;604,1/16W,1% ,0603,SMT R595,R596 

271071634211 RES;63.4K,1/16W,1% ,0603,SMT PR80 

271071681301 RES;680 ,1/16W,5% ,0603,SMT R75 

271071684101 RES;680K ,1/16W,1% ,0603,SMT PR27 

271071683101 RES;68K ,1/16W,1% ,0603,SMT 

271071698311 RES;698K ,1/16W,1% ,0603,SMT R22 


144



271071751101 RES;750 ,1/16W,1% ,0603,SMT R180 

271071750311 RES;750K,1/16W,1% ,0603,SMT PR84 

271071787311 RES;787K ,1/16W,1% ,0603,SMT PR16 

271071806111 RES;8.06K,1/16W,1% ,0603,SMT PR100,PR527 

271071822301 RES;8.2K ,1/16W,5% ,0603,SMT R103,R104,R123,R132,R150,R152 

271071806211 RES;80.6K,1/16W,1% ,0603,SMT PR72 

271071887211 RES;88.7K,1/16W,1% ,0603,SMT 

271071909011 RES;909 ,1/16W,1% ,0603,SMT 

451675300031 ROM ME KIT;8080 

271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP3,RP46 

271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SM RP10,RP42,RP43,RP44,RP8,RP9 

271571100301 RP;10*8 ,16P ,1/16W,5% ,1606,SM RP11,RP13,RP15,RP17,RP20,RP2 

271611272301 RP;2.7K*4,8P ,1/16W,5% ,0612,SMT RP6 

271621472302 RP;4.7K*8,10P,1/32W,5% ,1206,SMT RP39,RP45,RP47,RP503,RP505,R 

271611473301 RP;47K*4 ,8P ,1/16W,5% ,0612,SMT RP5 

271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP41,RP502 

271611560301 RP;56*4 ,8P ,1/16W,5% ,0612,SMT RP23,RP27,RP29 

271571560302 RP;56*8 ,16P,1/16W,5% ,1606,SMT RP12,RP14,RP16,RP18,RP19,RP2 

271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP501 

271611822301 RP;8.2K*4,8P ,1/16W,5% ,0612,SMT RP1,RP2,RP4,RP7 

345503400501 RUBBER;3MM,ROUND,8175 

345675300015 RUBBER;M-B, 8080 

345675300006 RUBBER;PAD DOWN,LCD,8080 

345675300004 RUBBER;PAD.UPPER,LCD,8080 

565167530001 S/W;CD ROM,SYSTEM DRIVER,8080 



340675300005 SCREW ASSY;CPU,8080 

341675300007 SHIELDING;HDD,8080 

333050000120 SHRINK TUBE;600V,105'C,D0.8*9MM, 

333050000107 SHRINK TUBE;UL,600V,105'C,ID2.5* 

561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY& 

361400003021 SOLDER CREAM;NOCLEAN,P4020870980 

361400003021 SOLDER CREAM;NOCLEAN,P4020870980 

365350000003 SOLDER WIRE;0.8MM,SN43/PB43/BI14 

600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC 

600100010005 SOLDER WIRE;63/37,0.8,NA,N/C,PRC 

370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 

370102630601 SPC-SCREW;M2.6L6,HDt0.5,NIWNLK 

370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK 

370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, 

370102010205 SPC-SCREW;M2L2(t0.3),N/W/WLK 

370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 

370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 

370102010309 SPC-SCREW;M2L3.0,NIW/NLK,HD07 

370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK 



370102010505 SPC-SCREW;M2L5,K-HD(t0.4),NIB,NL 



370102010702 SPC-SCREW;M2L7,K-HD,NLK,NIW 

145



370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3 

340675300026 SPEAKER ASSY; R, 8080 

340675300004 SPEAKER ASSY;L, 8080 

226600030332 SPONGE;320*290*10,CAIMAN,PWR 

377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW 

341675300008 STANDOFF;CPU,8080 MTG12,MTG13,MTG14,MTG15 

341675300009 STANDOFF;MDC,8080 MTG3,MTG4 

297120101005 SW;DIP,SPST,8P,50VDC,.1A,SMT,DHS SW2 

297040100013 SW;MINIATURE SLIDE,300MA,4V,7P,S SW501 

297040105012 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW3,SW4,SW5,SW6,SW7,SW8 

297040200004 SW;PUSH BUTTON,4P,12V/50MA,PT-03 SW502,SW503,SW504,SW505,SW 

297120100009 SW;SPST,4P,24VDC,50MA,STS-KD5,HC SW1 

297030102001 SW;TOGGLE,SPST,5V/0.2mA,H10.7MM, SW2 

225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U 

225600000310 TAPE;ADHENSIVE,DOUBLE-FACE,W8,UL 

622200000008 TAPE;CARTON,2.5"W,30M/RL,PRC 

225600000054 TAPE;INSULATING,POLYESTER FILM,1 

335612000004 THERMAL CUTOFFS;378,8A/50VDC,139 

442167530001 TOUCH PAD MODULE;TM41PUR2311-2,S 

288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES PQ11,PQ12,PQ14,PQ15,PQ16,PQ 

288227002001 TRANS;2N7002LT1,N-CHANNEL FET,SO Q15,Q16,Q515,Q516,Q517 

288204900001 TRANS;AO4900,DUAL N-MOSFET WITH PU16,PU17,PU19,PU5 

628820014401 TRANS;DTA144EKA,PNP,100MA,50V,SO Q3,Q5 

288200144002 TRANS;DTA144WK,PNP,SMT PQ508,Q513 

288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 Q10,Q13,Q17,Q18,Q19,Q21,Q25,Q 



288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT PQ503,Q20,Q23,Q24,Q34,Q5,Q51 

288206694002 TRANS;FDS6694,N-MOSFET,SO8,SMT PU507,PU509 

288207822001 TRANS;IRF7822,N-MOSFET,.005OHM,S PU20,PU501,PU504,PU56 

288202222001 TRANS;MMBT2222AL,NPN,TO236AB PQ506 

288203906002 TRANS;MMBT3906L,40V,200mA,SOT23, 

288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 Q1,Q22,Q37,Q511,Q512 

288204532001 TRANS;SI4532DY,N&P-MOSFET,SO8,PR 

288204788001 TRANS;SI4788CY,P-MOS,5A1.8~5.5V, U14,U23,U24,U25,U27 

288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU14,PU15,PU18,PU21,Q4 

288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM, PU503 

288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PQ5,PQ501,PQ502,PQ504 

288204925001 TRANS;SI4925DY,P-MOSFET,SO-8 PU1 

288208103001 TRANS;TPC8103,11A/30V,P-MOSFET,S Q1,Q1A,Q2,Q2A 

270140000003 VARISTOR;280V,5.6X3.8MM,TVB280-0 S1 

421675300010 WIRE ASSY;ANTENNA,8080 

421675300009 WIRE ASSY;INVERT,8080 

421675300014 WIRE ASSY;LI,3V,RTC BATTERY,CR20 

421675300011 WIRE ASSY;MDC,8080 

421675300005 WIRE ASSY;QDI,14,8080 

332110020111 WIRE;#20,UL1007,120MM,RED,YIYI;P 

332110020162 WIRE;#20,UL1007,45MM,RED,YIYI,PW 

332110020093 WIRE;#20,UL1007,55MM,BLK,YIYI;PW 

332110028161 WIRE;#28,UL1061,132MM,YELLOW,YIY 

332110028164 WIRE;#28,UL1061,26MM,BLACK,YIYI, 

332110028162 WIRE;#28,UL1061,28MM,WHITE,YIYI, 

146



332110028163 WIRE;#28,UL1061,80MM,BLUE,YIYI,P 

273001050039 XSFORMER;10/100 BASE,LF-H80P,SMT U11 

273001050062 XSFORMER;CI8.5,SIT16260,16/2600T 

274011431408 XTAL;14.318M,50PPM,32PF,7*5,4P,S X2 

274011431424 XTAL;14.318MHZ,20PPM,20PF,7*5,SM X501 

274011600408 XTAL;16MHZ,16PF,50PPM,8*4.5,2P X502 

274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X3 

274012500401 XTAL;25MHZ,30PPM,18PF,4P,SMT X4 

274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20 X1 


P/N:526267530024 

147

5 

8080_R03 

Project Code : G038 

5 

4 

PAGE03 Banais 

Clock Generator 

PLL207-151 

H8 

SMB Thermal Sensor 

ADM1021A 

CPU 

Intel Banais 

Micro-FCPGA 

PAGE04 Clock generator 

PAGE05 Montara-GM GMCH(1) 

PAGE06 

PAGE07 SO-DIMM 

FSB 

PAGE08 

PAGE09 

TV Encoder 

ICH4-M(1) 

CRT Connector 

RGB 

PAGE10 

PAGE11 HDD & CD-ROM 

200/266-MHz 

PAGE12 

PAGE13 

Audio Codec 

OP AMP 

TFT Flat Panel 

LVDS 

Montara-GM 

GMCH 

PAGE14 LCD & CRT connector 

PAGE15 

PAGE16 

IEEE1394a controller 

Ethernet controller 

732 pin 

Micro-FCBGA 

PAGE17 

PAGE18 

Mini PCI & USB & QSB 

CardBus & Card Reader controller 

TV Out Connector 

(S-Video or AV) 

CH7011A 

PAGE19 

PAGE20 

Super I/O & RS-232 

Embedded Controller 

PAGE21 Inverter & BIOS & TouchPad 

Hub Interface 

PAGE22 Power interface 

PAGE23 ADINP 

PCI Bus 

PAGE24 

PAGE25 

PAGE26 

PAGE27 

PAGE28 

PAGE29 

Charging 

+3V & +5V 

+1.5V & +1.8V 

+1.25V & +2.5V 

+1.05V & +1.2V 

CPU core 

CardBus & Card 

Reader 

CB710 

Power Switch 

CP2211 

ICH4-M 

421 pin BGA 

P-IDE 

S-IDE 

HDD 

CD-ROM 

DVOC 

PAGE01 

PAGE02 

Block Diagram 

Mounting Hole 

Montara-GM GMCH(2) 

ICH4-M(2) 

1394a port 

VT6307L 

4 in 1 slot 

RJ-45 

VT6105LOM 

USB 

Connector 

USB2.0*3 

4 

3 

D D 

C C 

B B 

D/D Power 

AC-Adapter 

+5V/+3V 

+2.5V/+1.25V 

+1.2V/+1.05V 

+1.5V/+1.8V 

D/D CPU Core 

BATT-Adapter 

PCMCIA Slot * 1 

+CPU_CORE 

Internal Speaker 

RJ-11 

Audio Amp 

APA0202ARI 

A A 

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 

3 

Line out & 

SPDIF 

MDC 

Daughtor Board 

AC'97 Codec 

EMP202 

Mic-in 

Connector 

System 

BIOS 

AC Link 

ISA Bus 

2 

2 

Super I/O 

PC87393 

LPC Bus 

Keyboard BIOS 

Hitachi 

H8/3437S 

PIO 

PS/2 

FIR 

KEY MATRIX 

EIGHT LED 

Title 

Size 

C 

Touch Pad 

Document 

Number 

1 

SO-DIMM * 2 

Internal 

Keyboard 


Rev 

411675300001 03 

Date: Friday, March 07, 2003 

1 

Sheet 1 of 29

VT6307L 

IDSEL: AD21 

PCI REQ0# 

PCI GNT0# 

PCI INTG# 

VT6105L 

IDSEL: AD18 

PCI REQ1# 

PCI GNT1# 

PCI INTE# 

5 

5 

4 

4 

3 

D D 

Mini PCI 

IDSEL: AD17 

PCI REQ3# 

PCI GNT3# 

PCI INTD# INTF# 

CB710 

IDSEL: AD20 

PCI REQ2# 

PCI GNT2# 

PCI INTB# INTF# 

8080 Stack Up 

4 mil 

6 mil 

7 mil 

6 mil 

7 mil 

6 mil 

4 mil 

Comp 

GND 

In1 

In2 

PWR 

In3 

GND 

Solder 

0.5 oz Cu 

0.5 oz Cu 

0.5 oz Cu 

0.5 oz Cu 

0.5 oz Cu 

0.5 oz Cu 

0.5 oz Cu 

0.5 oz Cu 

C C 

B B 

4 

5 

6 

3 

2 

1 

7 

8 

9 

MTG2 

ID3.0/OD6.5 

12 

11 

10 

GND GND 

GND 

AGND 

AGND 

GND 

GND 

GND 

3 

2 

REV Change detail 

DATE 

R00 

R01 

R02 

Initail release (base on Banias + Odem + ICH4-M) 

1.Correcting the error pin definition in EVT(include DIMM, HDD, 

KBD & TV connector) 

2.Add +3V_P for VT6105LOM to support wake on LAN. 

3.Add +5V_HDD to reduce the power consumption when into Audio 

DJ mode. 

4.Add +5V_CDROM to support IDE device hot swappable. 

5.Add R535 to support Intel Wireless module power down function 

using quick key. 

6.Remove Q21 & R291 to solve the card reader function fail. 

7.Reserve the spreading spectrum circuit for EMI. 

8.Change the DIMM connector from standard type to reverse type 

to solve the interfere problem. 

1.Add +5V_P to solve some USB2.0 device be downgrade to USB1.1 

when resume from S3. 

2. Reserve RS232 for S/W debugging if necessary. 

GND GND GND GND GND GND GND GND GND USB_GND 

MTG14 

MTG15 

GND GND GND GND GND GND GND GND GND GND 

ID4.5/OD7.0 

ID4.5/OD7.0 

TP516 TP501 TP505 TP540 TP541 

MTG7 

MTG9 

MTG10 

ID2.8/OD6.5 

ID2.8/OD6.5 

ID2.8/OD6.5 

4 

12 

4 

12 

4 

12 

13 

13 

TP19 TP520 TP22 TP16 TP23 TP8 TP519 TP12 TP9 TP18 

A 5 

11 

5 

11 

5 

11 

4 

12 

4 

12 

A 

6 

10 

6 

10 

6 

10 

5 

11 

5 

11 

6 

10 

6 

10 

GND GND GND AGND AGND 

3 

2 

1 

7 

8 

9 

4 

5 

6 

3 

2 

1 

7 

8 

9 

3 

2 

1 

7 

8 

9 

MTG3 

ID3.0/OD6.5 

12 

11 

10 

GND 

3 

2 

1 

7 

8 

9 

MTG5 

ID3.0/OD6.5 

12 

11 

10 

4 

5 

6 

MTG16 

ID2.2/OD6.5 

1 

3 

2 

1 

7 

8 

9 

GND 

13 

12 

11 

10 

GND 

MTG4 

ID2.2/OD6.5 

1 

MTG12 

ID4.5/OD7.0 

MTG6 

ID2.2/OD6.5 


4 

5 

6 

3 

2 

1 

7 

8 

9 

3 

2 

1 

7 

8 

9 

1 

4 

5 

6 

3 

2 

1 

7 

8 

9 

3 

2 

1 

7 

8 

9 

13 

12 

11 

10 

GND 

GND 

MTG13 

ID4.5/OD7.0 


1 

1 

1 

1 

1 

1 


1 

1 

1 

1 

1 

1 

1 

1 

1 

GNDGND_45 

GND GND GND GND GND GNDTV_GND 

GND 

1 

1 

1 

1 

1 

1 

2 

1 

1 

1 

1 

1 

1 

1 

1 

1 

FD503 

1 

FD4 

1 

1 

FD504 

1 

FD1 

1 

Title 

Size 

C 

1 

1 

Document 

Number 

FD501 

1 

FD3 

1 

1 

1 

1 

2002/10/28 

2002/12/16 

2003/01/28 

FD502 


ECR No. 

Rev 

411675300001 03 


1 

Sheet 2 of 29 

1 

FD2 

1

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

VCCP : PROCESSOR I/O POWER SUPPLY. 

Slave Address 0011000 

Close to CPU as possible. 

PLACEMENT MAX. 3" FROM CPU. 

Don't overlay by CHOKE or vibrating signals. 

Place thermal sensor as close to 

VGA as possible for the critical 

of VGA chip thermal issue. 

Core power decoupling 

(1.05V) 

1.8V, Option to 1.5V 

for future support. 

VCC : PROCESSOR CORE POWER SUPPLY. 

Close to CPU as possible. 

VCCA : ISOLATE POWER FOR INTERNAL PLL. 

VCCQ : QUIET POWER SUPPLY FOR ON DIE COMP CKT. 

HCOMP0 & HCOMP2 should be 

route with 18 mil width 

HCOMP1 & HCOMP3 should be 


411675300001 03 


C 

3 29 

Friday, March 07, 2003 

Title 

Size 

Document 

Number 

Rev 

Date: Sheet of 

HD#5 

HA#10 

HA#20 

HDSTBN#0 

HSMI# 

HD#12 

VID2 

HA20M# 

HTRST# 

HD#46 

HDINV#[0..3] 

HD#16 

HD#13 

HA#14 

HINIT# 

HREQ#0 

HD#18 

HD#2 

HA#16 

HD#60 

HA#28 

HCOMP0 

HDBR# HD#59 

HD#42 

HD#33 

HDSTBN#[0..3] 

HD#62 

HSTPCLK# 

HDSTBP#2 

HD#38 

CPU_TEST2 

HD#4 

HCOMP0 

HA#7 

HD#11 

HA#22 

CPU_THERMDC 

HDSTBN#1 

HPWRGD 

HD#14 

VID5 

HD#55 

CPU_THERMDA 

HBR0# 

HPREQ# 

VID1 

HD#34 

HA#19 

HREQ#4 

HD#29 

HD#27 

VID[0..5] 

HPWRGD 

HD#9 

HDINV#2 

HSLP# 

HRS#1 HD#53 

HD#22 

HD#50 

HA#30 

HIGNNE# 

CPU_TEST3 

HTCLK 

HA#18 

HA#4 

HA#27 

HRS#[0..2] 

HCOMP1 

HDSTBN#2 

HA#26 

HD#21 

HD#25 

HD#51 

HD#40 

VID3 

HRS#0 

HD#39 

HD#45 

HREQ#3 

HCOMP1 

HDSTBP#3 

HDPSLP# 

HD#6 

HD#20 

HPROCHOT# 

HTDI 

VID4 

CPU_THERMDC 

HPRDY# 

HD#8 

HDINV#3 

HD#58 

HRS#2 

HD#61 

HD#3 

TEMP_ALERT# 

CPU_TEST1 

HA#9 

HA#25 

HCOMP2 

HDSTBN#3 

HA#31 

HA#15 

HD#26 

HSLP# 

HD#35 

HBPM#0 

HREQ#2 

HCOMP3 

HA#23 

HINTR 

HA#5 

HD#28 

HSTPCLK# 

HINTR 

HD#17 

HTDO 

HDINV#0 

HD#63 

HD#57 

HINIT# 

HD#36 

HD#19 

HD#10 

HA#13 

HD#56 

HD#[0..63] 

HBPM#1 

HPSI# 

HA20M# 

HDSTBP#0 

HD#52 

HD#1 

CPU_TEST3 

HA#24 

HCOMP3 

HDSTBP#[0..3] 

HD#43 

HD#24 

HBR0# 

HREQ#[0..4] 

HD#47 

HA#[3..31] 

HREQ#1 

HD#7 

HA#8 

HCOMP2 

HA#21 

HNMI 

HIGNNE# 

HD#23 

HA#29 

CPU_TEST1 

HTMS 

HDINV#1 

HD#31 

HD#15 

HA#12 

HDPSLP# 

HA#3 

HNMI 

HD#30 

HDBR# 

HA#6 

HD#0 

HA#11 

CPU_TEST2 

CPU_THERMDA 

HD#48 

HPROCHOT# 

HD#54 

HD#37 

HD#44 

HD#41 

VID0 

HSMI# 

HD#49 

HDSTBP#1 

HD#32 

HA#17 

TEMP_ALERT# 

+VCC_CORE 

+VCC_CORE 

GND 

+VCC_CORE 

+VCCA 

GND 

+VCCP 

+3V 

GND 

+VCCP 

+1.5V 

+VCCQ 

GND 

+VCC_CORE 

GND 

+VCC_CORE 

+VCCP 

+VCCA 

+VCC_CORE 

+VCCP 

GND 

GND 

GND 

+VCCP 

+VCCP 

+VCCP 

GND 

+1.8V 

GND 

+VCC_CORE 

+3V 

+VCCQ 

GND 

+3V_P 

+VCCP 

GND 

GND 

GND 

+VCC_CORE 

+VCCP 

GND 

+VCCP 

GND 

+3V_P 

+VCCP 

GND 

+3V_P 

C18 

0.1U 

50V 

0603 

1 

2 

C30 

0.1U 

50V 

0603 

1 

2 

R17 

0/NA 0603 

1 2 

C501 

10U 

10V 

1206 

1 

2 

R513 

0/NA 0603D_DFS 

1 2 

R506 

200/NA 0603 

1 2 

C8 

0.1U 

50V 

0603 

1 

2 

R11 

10K/NA 

0603 

1 

2 

C91 

220P 

0603 

10% 

1 

2 

C37 

10U 

10V 

1206 

1 

2 

C21 

0.1U 

50V 

0603 

1 

2 

C47 

0.1U 

50V 

0603 

1 

2 

C28 

10U 

10V 

1206 

1 

2 

R16 


1 2 

L10 0/NA 0603D 

1 2 

C43 

10U 

10V 

1206 

1 

2 

L6 0 0805C 

1 2 

C79 

10U 

10V 

1206 

1 

2 

C74 

10U 

10V 

1206 

1 

2 

R10 

10K 

0603 

1 

2 

C51 

10U 

10V 

1206 

1 

2 

R1 

Q2 

DTC144TKA/NA 

2 

1 3 

C44 

10U 

10V 

1206 

1 

2 

R94 

1K 

0603 1% 

1 2 

C78 

0.1U 

50V 

0603 

1 

2 

R21 

200/NA 0603 

1 2 

L7 

120Z/100M 

2012 

1 2 

C23 

0.1U 

50V 

0603 

1 

2 

C70 

10U 

10V 

1206 

1 

2 

C24 

10U 

10V 

1206 

1 

2 

U501B 

BANIAS 

BGA479_SKT3 

D6 

D8 

D18 

D20 

D22 

E5 

E7 

E9 

E17 

E19 

E21 

F6 

F8 

F18 

F20 

F22 

G5 

G21 

H6 

H22 

J5 

J21 

K22 

U5 

V6 

V22 

W5 

W21 

Y6 

Y22 

AA5 

AA7 

AA9 

AA11 

AA13 

AA15 

AA17 

AA19 

AA21 

AB6 

AB8 

AB10 

AB12 

AB14 

AB16 

AB18 

AB20 

AB22 

AC9 

AC11 

AC13 

AC15 

AC17 

AC19 

AD8 

AD10 

AD12 

AD14 

AD16 

AD18 

AE9 

B15 

B14 

AC1 

A9 

C9 

B8 

C8 

A13 

C12 

A12 

C11 

B13 

B10 

A10 

AD26 

E26 

G1 

AF7 

C14 

C3 

C5 

F23 

C16 

P25 

P26 

AB2 

AB1 

D25 

J26 

T24 

AD20 

AE11 

AE13 

AE15 

AE17 

AE19 

AF8 

AF10 

AF12 

AF14 

AF16 

AF18 

VCC_0 

VCC_1 

VCC_2 

VCC_3 

VCC_4 

VCC_5 

VCC_6 

VCC_7 

VCC_8 

VCC_9 

VCC_10 

VCC_11 

VCC_12 

VCC_13 

VCC_14 

VCC_15 

VCC_16 

VCC_17 

VCC_18 

VCC_19 

VCC_20 

VCC_21 

VCC_22 

VCC_23 

VCC_24 

VCC_25 

VCC_26 

VCC_27 

VCC_28 

VCC_29 

VCC_30 

VCC_31 

VCC_32 

VCC_33 

VCC_34 

VCC_35 

VCC_36 

VCC_37 

VCC_38 

VCC_39 

VCC_40 

VCC_41 

VCC_42 

VCC_43 

VCC_44 

VCC_45 

VCC_46 

VCC_47 

VCC_48 

VCC_49 

VCC_50 

VCC_51 

VCC_52 

VCC_53 

VCC_54 

VCC_55 

VCC_56 

VCC_57 

VCC_58 

VCC_59 

VCC_60 

BCLK0 

BCLK1 

GTLREF3 

BPM2# 

BPM3# 

BPM1# 

BPM0# 

TCK 

TDI 

TDO 

TMS 

TRST# 

PREQ# 

PRDY# 

GTLREF0 

GTLREF1 

GTLREF2 

RSVD_0 

RSVD_2 

RSVD_3 

TEST1 

TEST2 

TEST3 

COMP0 

COMP1 

COMP2 

COMP3 

DINV0# 

DINV1# 

DINV2# 

DINV3# 

VCC_61 

VCC_62 

VCC_63 

VCC_64 

VCC_65 

VCC_66 

VCC_67 

VCC_68 

VCC_69 

VCC_70 

VCC_71 

C69 

10U 

10V 

1206 

1 

2 

C72 

10U 

10V 

1206 

1 

2 

R24 

54.9 

0603 

1% 

1 2 

TP502 1 

R503 56 

0603 

1 2 

R505 

200/NA 0603 

1 2 

C15 

0.1U 

50V 

0603 

1 

2 

C46 

0.1U 

50V 

0603 

1 

2 

R36 


1 2 

R504 

200/NA 0603 

1 2 

R507 

1K 

0603 1% 

1 2 

C34 

10U 

10V 

1206 

1 

2 

C88 

10U 

10V 

1206 

1 

2 

R522 

56 

0603 

1 

2 

C84 

10U 

10V 

1206 

1 

2 

C16 

10U 

10V 

1206 

1 

2 

R23 

0/NA 

0603D_DFS 

1 

2 

R521 

1K 

0603 1% 

1 2 

C65 

0.1U 

50V 

0603 

1 

2 

C80 

0.1U 

50V 

0603 

1 

2 

U501A 

BANIAS 

BGA479_SKT3 

P4 

U4 

V3 

R3 

V2 

W1 

T4 

W2 

Y4 

Y1 

U1 

AA3 

Y3 

AA2 

AF4 

AC4 

AC7 

AC3 

AD3 

AE4 

AD2 

AB4 

AC6 

AD5 

AE2 

AD6 

AF3 

AE1 

AF1 

R2 

P3 

T2 

P1 

T1 

U3 

N2 

AE5 

A4 

A19 

A25 

A22 

B21 

A24 

B26 

A21 

B20 

C20 

B24 

D24 

E24 

C26 

B23 

E23 

C25 

H23 

G25 

L23 

M26 

H24 

F25 

G24 

J23 

M23 

J25 

L26 

N24 

M25 

H26 

N25 

K25 

Y26 

AA24 

T25 

U23 

V23 

R24 

R26 

R23 

AA23 

U26 

V24 

U25 

V26 

Y23 

AA26 

Y25 

AB25 

AC23 

AB24 

AC20 

AC22 

AC25 

AD23 

AE22 

AF23 

AD24 

AF20 

AE21 

AD21 

AF25 

AF22 

AF26 

C23 

K24 

W25 

AE24 

C22 

L24 

W24 

AE25 

M2 

H2 

B18 

A18 

A7 

B5 

B11 

D1 

D4 

C6 

B7 

C2 

D3 

A3 

B4 

E4 

H1 

K1 

L2 

M3 

K3 

K4 

L4 

N4 

J3 

L1 

J2 

C19 

B17 

E1 

A6 

C17 

A16 

A15 

A3# 

A4# 

A5# 

A6# 

A7# 

A8# 

A9# 

A10# 

A11# 

A12# 

A13# 

A14# 

A15# 

A16# 

A17# 

A18# 

A19# 

A20# 

A21# 

A22# 

A23# 

A24# 

A25# 

A26# 

A27# 

A28# 

A29# 

A30# 

A31# 

REQ0# 

REQ1# 

REQ2# 

REQ3# 

REQ4# 

ADSTB0# 

ADS# 

ADSTB1# 

IERR# 

D0# 

D1# 

D2# 

D3# 

D4# 

D5# 

D6# 

D7# 

D8# 

D9# 

D10# 

D11# 

D12# 

D13# 

D14# 

D15# 

D16# 

D17# 

D18# 

D19# 

D20# 

D21# 

D22# 

D23# 

D24# 

D25# 

D26# 

D27# 

D28# 

D29# 

D30# 

D31# 

D32# 

D33# 

D34# 

D35# 

D36# 

D37# 

D38# 

D39# 

D40# 

D41# 

D42# 

D43# 

D44# 

D45# 

D46# 

D47# 

D48# 

D49# 

D50# 

D51# 

D52# 

D53# 

D54# 

D55# 

D56# 

D57# 

D58# 

D59# 

D60# 

D61# 

D62# 

D63# 

DSTBN0# 

DSTBN1# 

DSTBN2# 

DSTBN3# 

DSTBP0# 

DSTBP1# 

DSTBP2# 

DSTBP3# 

DBSY# 

DRDY# 

THERMDA 

THERMDC 

DBR# 

INIT# 

RESET# 

LINT0 

LINT1 

STPCLK# 

DPSLP# 

A20M# 

FERR# 

IGNNE# 

SMI# 

PWRGOOD 

RS0# 

RS1# 

RS2# 

TRDY# 

HIT# 

HITM# 

DEFER# 

BR0# 

BPRI# 

BNR# 

LOCK# 

DPWR# 

PROCHOT# 

PSI# 

SLP# 

THERMTRIP# 

ITP_CLK0 

ITP_CLK1 

C56 

10U 

10V 

1206 

1 

2 

R502 

200/NA 0603 

1 2 

C54 

10U 

10V 

1206 

1 

2 

C58 

10U 

10V 

1206 

1 

2 

C90 

1U 

0603 

1 

2 

C106 

0.1U 

50V 

0603 

1 

2 

C76 

10U 

10V 

1206 

1 

2 

C31 

0.1U 

50V 

0603 

1 

2 

C75 

10U 

10V 

1206 

1 

2 

R49 

200 0603 

1 2 

C57 

10U 

10V 

1206 

1 

2 

C14 

2.2U 

16V 

1206 

1 

2 

C71 

10U 

10V 

1206 

1 

2 

C503 

10U 

10V 

1206 

1 

2 

R9 0/NA 

0603D_DFS 

1 2 

C17 

0.1U 

50V 

0603 

1 

2 

R87 

1K 

0603 

1% 

1 

2 

R53 

200/NA 0603 

1 2 

C505 

10U 

10V 

1206 

1 

2 

C83 

10U 

10V 

1206 

1 

2 

C52 

10U 

10V 

1206 

1 

2 

C48 

0.1U 

50V 

0603 

1 

2 

C45 

0.1U 

50V 

0603 

1 

2 

C19 

0.1U 

50V 

0603 

1 

2 

U1 

ADM1021A QSOP16B 

1 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

2 

TEST 

D+ 

D- 

NC1 

ADD1 

GND1 

GND2 

NC2 

ADD0 

ALERT 

SDATA 

NC3 

SCLK 

STBY 

TEST1 

VDD 

C22 

10U 

10V 

1206 

1 

2 

C61 

0.1U 

50V 

0603 

1 

2 

R20 

200/NA 0603 

1 2 

C89 

0.1U 

50V 

0603 

1 

2 

C35 

10U 

10V 

1206 

1 

2 

C10 

2200P 

0603 

1 

2 

R96 

54.9 

0603 

1% 

1 2 

R15 

10K 

0603 

1 

2 

C41 

10U 

10V 

1206 

1 

2 

C77 

0.1U 

50V 

0603 

1 

2 

C73 

10U 

10V 

1206 

1 

2 

C502 

10U 

10V 

1206 

1 

2 

R88 

2K 

0603 

1% 

1 

2 

U501D 

BANIAS 

BGA479_SKT3 

AD1 

AC8 

AC10 

AC12 

AC14 

AC16 

AC18 

AC21 

AC24 

E2 

F2 

F3 

G3 

G4 

H4 

D10 

D12 

D14 

D16 

E11 

E13 

E15 

F10 

F12 

F14 

F16 

K6 

L5 

L21 

M6 

M22 

N5 

N21 

P6 

P22 

R5 

R21 

T6 

T22 

P23 

W4 

AE7 

F26 

B1 

N1 

AC5 

AC2 

AB26 

AB23 

AB21 

AB19 

AD4 

AD7 

AD9 

AD11 

AD13 

U21 

AE8 

AE6 

AE3 

AD25 

AD22 

AD19 

AD17 

AD15 

AE10 

AE12 

AE14 

AE16 

AE18 

AE20 

AE23 

AE26 

AF2 

AF5 

AF9 

AF11 

AF13 

AF15 

AF17 

AF19 

AF21 

AF6 AF24 

AC26 

VSS_160 

VSS_152 

VSS_153 

VSS_154 

VSS_155 

VSS_156 

VSS_157 

VSS_158 

VSS_159 

VID0 

VID1 

VID2 

VID3 

VID4 

VID5 

VCCP_0 

VCCP_1 

VCCP_2 

VCCP_3 

VCCP_4 

VCCP_5 

VCCP_6 

VCCP_7 

VCCP_8 

VCCP_9 

VCCP_10 

VCCP_11 

VCCP_12 

VCCP_13 

VCCP_14 

VCCP_15 

VCCP_16 

VCCP_17 

VCCP_18 

VCCP_19 

VCCP_20 

VCCP_21 

VCCP_22 

VCCP_23 

VCCQ0 

VCCQ1 

VCCSENSE 

VCCA0 

VCCA1 

VCCA2 

VSS_151 

VSS_150 

VSS_149 

VSS_148 

VSS_147 

VSS_146 

VSS_161 

VSS_162 

VSS_163 

VSS_164 

VSS_165 

VCCP_24 

VSS_173 

VSS_172 

VSS_171 

VSS_170 

VSS_169 

VSS_168 

VSS_167 

VSS_166 

VSS_174 

VSS_175 

VSS_176 

VSS_177 

VSS_178 

VSS_179 

VSS_180 

VSS_181 

VSS_182 

VSS_183 

VSS_184 

VSS_185 

VSS_186 

VSS_187 

VSS_188 

VSS_189 

VSS_190 

VSSENSE VSS_191 

VCCA3 

C507 

10U 

10V 

1206 

1 

2 

C26 

0.1U 

50V 

0603 

1 

2 

R28 

51 

0603 

1 

2 

C42 

10U 

10V 

1206 

1 

2 

C66 

10U 

10V 

1206 

1 

2 

C33 

0.1U 

50V 

0603 

1 

2 

C67 

0.1U 

50V 

0603 

1 

2 

R22 

300 

0603 

1 

2 

R501 

10K/NA 

0603 

1 2 

C85 

10U 

10V 

1206 

1 

2 

C29 

10U 

10V 

1206 

1 

2 

C20 

10U 

10V 

1206 

1 

2 

C62 

0.1U 

50V 

0603 

1 

2 

R26 

54.9 

0603 

1% 1 2 

R98 

27.4 

0603 

1 2 

C59 

10U 

10V 

1206 

1 

2 

C53 

10U 

10V 

1206 

1 

2 

R14 

0/NA 

0603D_DFS 

1 

2 

U501C 

BANIAS 

BGA479_SKT3 

A2 

A5 

A8 

A11 

A14 

A17 

A20 

A23 

A26 

B3 

B6 

B9 

B12 

B16 

B19 

B22 

B25 

C1 

C4 

C7 

C10 

C13 

C15 

C18 

C21 

C24 

D2 

D5 

D7 

D9 

D11 

D13 

D15 

D17 

D19 

D21 

D23 

D26 

E3 

E6 

E8 

E10 

E12 

E14 

E16 

E18 

E20 

E22 

E25 

F1 

F4 

F5 

F7 

F9 

F11 

F13 

F15 

F17 

F19 

F21 

F24 

G2 

G6 

G22 

G23 

G26 

H3 

H5 

H21 

H25 

J1 

J4 

J6 

J22 

J24 

K2 

K5 

K21 

K23 

K26 

L3 

L6 

L22 

L25 

M1 

M4 

M5 

M21 

M24 

N3 

N6 

N22 

N23 

N26 

P2 

P5 

P21 

P24 

R1 

R4 

R6 

R22 

R25 

T3 

T5 

T21 

T23 

T26 

U2 

U6 

U22 

U24 

V1 

V4 

V5 

V21 

V25 

W3 

W6 

W22 

W23 

W26 

Y2 

Y5 

Y21 

Y24 

AA1 

AA4 

AA6 

AA8 

AA10 

AA12 

AA14 

AA16 

AA18 

AA20 

AA22 

AA25 

AB3 

AB5 

AB7 

AB9 

AB11 

AB13 

AB15 

AB17 

VSS_0 

VSS_1 

VSS_2 

VSS_3 

VSS_4 

VSS_5 

VSS_6 

VSS_7 

VSS_8 

VSS_9 

VSS_10 

VSS_11 

VSS_12 

VSS_13 

VSS_14 

VSS_15 

VSS_16 

VSS_17 

VSS_18 

VSS_19 

VSS_20 

VSS_21 

VSS_22 

VSS_23 

VSS_24 

VSS_25 

VSS_26 

VSS_27 

VSS_28 

VSS_29 

VSS_30 

VSS_31 

VSS_32 

VSS_33 

VSS_34 

VSS_35 

VSS_36 

VSS_37 

VSS_38 

VSS_39 

VSS_40 

VSS_41 

VSS_42 

VSS_43 

VSS_44 

VSS_45 

VSS_46 

VSS_47 

VSS_48 

VSS_49 

VSS_50 

VSS_51 

VSS_52 

VSS_53 

VSS_54 

VSS_55 

VSS_56 

VSS_57 

VSS_58 

VSS_59 

VSS_60 

VSS_61 

VSS_62 

VSS_63 

VSS_64 

VSS_65 

VSS_66 

VSS_67 

VSS_68 

VSS_69 

VSS_70 

VSS_71 

VSS_72 

VSS_73 

VSS_74 

VSS_75 

VSS_76 

VSS_77 

VSS_78 

VSS_79 

VSS_80 

VSS_81 

VSS_82 

VSS_83 

VSS_84 

VSS_85 

VSS_86 

VSS_87 

VSS_88 

VSS_89 

VSS_90 

VSS_91 

VSS_92 

VSS_93 

VSS_94 

VSS_95 

VSS_96 

VSS_97 

VSS_98 

VSS_99 

VSS_100 

VSS_101 

VSS_102 

VSS_103 

VSS_104 

VSS_105 

VSS_106 

VSS_107 

VSS_108 

VSS_109 

VSS_110 

VSS_111 

VSS_112 

VSS_113 

VSS_114 

VSS_115 

VSS_116 

VSS_117 

VSS_118 

VSS_119 

VSS_120 

VSS_121 

VSS_122 

VSS_123 

VSS_124 

VSS_125 

VSS_126 

VSS_127 

VSS_128 

VSS_129 

VSS_130 

VSS_131 

VSS_132 

VSS_133 

VSS_134 

VSS_135 

VSS_136 

VSS_137 

VSS_138 

VSS_139 

VSS_140 

VSS_141 

VSS_142 

VSS_143 

VSS_144 

VSS_145 

R38 

200/NA 0603 

1 2 

C63 

10U 

10V 

1206 

1 

2 

R27 

54.9 

0603 

1% 1 2 

C64 

0.1U 

50V 

0603 

1 

2 

C68 

10U 

10V 

1206 

1 

2 

R25 

27.4 

0603 

1 2 

R19 

200/NA 0603 

1 2 

C509 

10U 

10V 

1206 

1 

2 

C32 

10U 

10V 

1206 

1 

2 

C27 

0.1U 

50V 

0603 

1 

2 

C512 

10U 

10V 

1206 

1 

2 

C50 

10U 

10V 

1206 

1 

2 

HLOCK# 

5 

HCLK_CPU 

4 

HDINV#[0..3] 

5 

HHITM# 

5 

HNMI 

9 

HFERR# 

10 

HINTR 

9 

HA20M# 

9 

HADSTB#1 

5 

CLK_ITP_CPU# 

4 

CLK_ITP_CPU 

4 

HSTPCLK# 

9 

HPWRGD 

9 

HSMI# 

9 

HCPURST# 

4,5 

HBPRI# 

5 

HIGNNE# 

9 

HD#[0..63] 5 

HA#[3..31] 

5 

HHIT# 

5 

HTRDY# 

5 

HADSTB#0 

5 

HSLP# 

9 

HDPSLP# 

5,9 

HDPWR# 

5 

HBR0# 

5 

HPREQ# 

4 

CPUPERF# 

9 

VID[0..5] 

29 

HADS# 

5 

HPRDY# 

4 

HTRST# 

4 

HTMS 

4 

HTDO 

4 

HTDI 

4 

HTCLK 

4 

HREQ#[0..4] 

5 

HDSTBN#[0..3] 5 

H8_THRM_DATA 20 

HBPM#0 

4 

H8_THRM_CLK 20 

CPU_THRMTRIP_OUT# 10 

HBPM#1 

4 

SUSB# 4,9,18,20,21,22,26,28,29 

HDSTBP#[0..3] 5 

HCLK_CPU# 

4 

HDBSY# 5 

HINIT# 

9 HDRDY# 5 

HDEFER# 

5 

HBNR# 

5 

HRS#[0..2] 

5 

TEMP_ALERT# 20 

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5 

0 

0 

0 

0 

5 

5 

0 

4 

4 

3 

D 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

1 

0 

0 

1 

0 

1.676 

1.660 

1.644 

1 

1 

1 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

1 

0 

0 

1 

0 

1.164 

1.148 

1.132 

3 HPREQ# 

3 HPRDY# 

3 HBPM#1 

3 HBPM#0 

3 HTDO 

3 HTMS 

R114 

4.7K 

0603 

R158 

4.7K 

0603 

R157 

4.7K/NA 

0603 

D 

0 0 0 1 0 1 1.628 

1 0 0 1 0 1 1.116 

3 HTDI 

3,5 HCPURST# 

0 0 0 1 1 0 1.612 

1 0 0 1 1 0 1.100 

3 HTRST# 

0 0 0 1 1 1 1.596 

1 0 0 1 1 1 1.084 

3 HTCLK 

GND 

0 

0 

0 

0 

0 

0 

0 

0 

0 

0 

4 

0 

0 

0 

0 

0 

0 

0 

0 

1 

1 

1 

VID 

3 

1 

1 

1 

1 

1 

1 

0 

2 

0 

0 

1 

1 

0 

0 

0 

1 

0 

0 

0 

0 

1 

0 

1 

0 

0 

0 

1 

VCC-Core 

1.708 

1.580 

1.532 

1.516 

1.484 

1.452 

1.436 

1 

1 

1 

1 

1 

1 

1 

1 

0 

0 

0 

0 

0 

1 

1 

VID 

3 

0 

1 

1 

1 

1 

1 

1 

0 

2 

0 

0 

0 

0 

1 

1 

1 

0 

0 

0 

0 

0 

0 

1 

0 

1 

0 

1 

1 

0 

0 

1 

1 

0 

0 

1 

1 

VCC-Core 

1.196 

1.180 

1.068 

1.052 

1.020 

0.940 

0.924 

0.908 

0.892 

Place close to CPU socket within 2". 

3 

2 

2 

FS2 

X 

X 

X 

X 

Mid 

Mid 

0:0V 

1:3.3V 

FS1 

0 

0 

1 1 133.33 66.66 

0 0 1 1 1 1 1.468 

1 0 1 1 1 1 0.956 

Mid 0 1 TCLK/2 TCLK/2 

1 

0 

0 

0 

0 

0 

0 

0 

0 

1 

0 

1 

1 

0 

1 

1 

1 

0 

0 

1 

1.692 

1.564 

0 0 1 0 1 0 1.548 

1 0 1 0 1 0 1.036 

0 

1 

0 

1 

2 

1.500 

1.420 

1.404 

5 

1 

1 

1 

1 

4 

0 

0 

0 

1 

1 

1 

2 

0 

0 

0 

0 

0 

1 

0 

0 

0 

0 

1 

1 

0 

0 

1 

2 

1.004 

0.988 

0.972 

0 1 0 1 0 0 1.388 

1 1 0 1 0 0 0.876 

48M_DREFCLK 5 

C 

0 

0 

0 

0 

1 

1 

1 

1 

0 

0 

0 

1 

1 

1 

1 

0 

0 

1 

1 

0 

1 

0 

1 

0 

1.372 

1.356 

1.340 

1.324 

1 

1 

1 

1 

1 

1 

1 

1 

0 

0 

0 

1 

1 

1 

1 

0 

0 

1 

1 

0 

1 

0 

1 

0 

0.860 

0.844 

0.828 

0.812 

X2 

1 3 

2 

4 

14.318MHZ 

R112 R111 R107 

33 33 33 

0603 0603 0603 

1 

0603 

10% 

2 C101 

10P/NA 

C105 

10P/NA 

0603 

10% 

USBCLK_ICH 10 

48M_SUPERIO 19 

VCH_CLK 

C 

0 1 1 0 0 1 1.308 

1 1 1 0 0 1 0.796 

C132 

33P 

C129 

33P 

1 2 C138 

0 1 1 0 1 0 1.292 

1 1 1 0 1 0 0.780 

0603 

50V 

0603 

50V 

0603 

10% 

10P/NA 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

GND 

+3V 

+3VCLKANA 

L14 

1 2 

+3V 

L517 

+3VCLKCPU 

GND 

C136 

0.1U 

0603 

50V 

120Z/100M 

2012 

C110 

0.1U 

0603 

50V 

C100 

0.1U 

0603 

50V 

C133 

0.1U 

0603 

50V 

C135 

2.2U 

0805 

+80-20% 

1 2 

120Z/100M 

C564 2012 

0.1U 

0603 

50V 

C128 

0.1U 

0603 

50V 

C119 

0.1U 

0603 

50V 

C553 

2.2U 

0805 

+80-20% 

VCH_CLK 

R240 

0/NA 

0603D_DFS 

A 

GND 

+3V 

L9 

+3VCLK66 

GND 

GND 

+3V 

L513 

1 2 

GND 

3,9,18,20,21,22,26,28,29 SUSB# 

+3VCLKPCI 

VCH_CLK 

1 2 

R360 0/NA 

SMBDATA 

SMBCLK 

1 

8 

6 

7 

U26 

CLKIN 

*PD# 

SDATA 

SCLK 

**CLKOUT/FS_IN0 

*REF_OUT/FS_IN1 

VDD 

GND 

4 

5 

2 

3 

R251 33/NA 

1 2 

1 2 

R291 10K/NA 

+3V 

66M_DEFSSCLK 5 

A 

1 2 

120Z/100M 

C99 2012 

0.1U 

0603 

50V 

C113 

0.1U 

0603 

50V 

C97 

0.1U 

0603 

50V 

C98 

2.2U 

0805 

+80-20% 

C535 

0.1U 

0603 

50V 

120Z/100M 

2012 

C122 

0.1U 

0603 

50V 

C117 

0.1U 

0603 

50V 

C542 

2.2U 

0805 

+80-20% 

ICS91718/NA 

SO8 

R329 

10K/NA 

0603 

Title 

GND 

GND 

GND 

GND 

GND 


Size 

C 

Document 

Number 

411675300001 

Rev 

03 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

4 

9 

15 

20 

27 

31 

36 

41 

47 

1 

2 

GND0 

GND1 

GND2 

GND3 

GND4 

GND5 

GND6 

GND7 

GND8 

PLL207-151 

TSSOP56 

R518 

51 

0603 

1 

2 

GND 

1 

2 

R520 

27.4 

0603 

R517 

51 

0603 

1 

2 

1 

2 

GND 

+VCC_CORE 

R512 

51 

0603 

1 

2 

R75 

680 

0603 

R37 

51 

0603 

42 

IREF 

1 

2 

1 

2 

1 

2 

+VCCP 

1 

R67 

51/NA 

0603 

2 

1 2 

1 

R65 

39 

0603 

R124 

475 

0603 

1% 

1 2 

2 

R60 

150 

0603 

1 

2 

1 2 

1 

2 

R56 

51 

0603 

1 

2 

1 

2 

1 

2 

1 

C103 

10P/NA 

0603 

10% 

2 

GND 

001 

1 

2 

C107 

10P/NA 

0603 

10% 

FS0 

FS1 

FS2 

1 

2 

1 

2 

C130 

10P/NA 

0603 

10% 

1 

2 

Mid 

1 

2 

1 

2 

1 

2 

1 

2 

1 

0 

1 

1 

1 

2 

1 

2 

FS0 

0 

1 

0 

0 

0 

1 

+3V 

1 

R113 R174 R173 

4.7K/NA 4.7K/NA 4.7K 

0603 0603 0603 

B 

0 1 1 0 1 1 

0 1 1 1 0 0 

0 1 1 1 0 1 

0 1 1 1 1 0 

0 1 1 1 1 1 

29 CORE_CLKEN# 

9,29 STOP_CPU# 

9 STOP_PCI# 

1.276 

1.260 

1.244 

1.228 

1.212 

0/NA 1 

0603D_DFS 

1 

0603 

1 

0603 

1 1 1 0 1 1 0.764 

1 1 1 1 0 0 0.748 

1 1 1 1 0 1 0.732 

1 1 1 1 1 0 0.716 

1 1 1 1 1 1 0.700 

+3V 

R81 

10K 

0603 

1% 

2 

VTT_PWRGD# 

R86 

2 R165 CLK_CPU_STOP# 

0/NA 

2 R102 CLK_PCI_STOP# 

0/NA 

GND 

Layout note: Place crystal within 

500 mils of CLK Gen. 

7,10,14 SMBDATA 

7,10,14 SMBCLK 

FS0 

FS1 

FS2 

R95 1 2 8.2K 0603D 

R104 CLK_PCI_STOP# 

+3V 

1 2 8.2K 0603D 

R166 1 2 8.2K 0603D CLK_CPU_STOP# 

8.2K 

+3V 

1 2 R541 

VTT_PWRGD# 

+3VCLKANA 

+3VCLK66 

+3VCLKCPU 

+3VCLKPCI 

U4 

2 

X1 

48MHZ_USB 

48MHZ_DOT 

3 

X2 

3V66_1/VCH_CLK 

29 

SDATA 

30 

SCLK 

REF 

54 

FS0 

55 

FS1 

CPUCLKT0 

40 

FS2 

CPUCLKT1 

CPUCLKT2 

25 

*PD# 

34 

PCI_STOP# 

CPUCLKC0 

53 

CPU_STOP#* 

CPUCLKC1 

CPUCLKC2 

43 

MULTSEL0* 

28 

VTT_PWRGD# 

PCICLK0 

PCICLK1 

1 

VDDREF 

PCICLK2 

37 

VDD48 

PCICLK3 

26 

VDDA 

PCICLK4 

19 

VDD3V66_0 

PCICLK5 

32 

VDD3V66_1 

PCICLK6 

46 

VDDCPU0 

50 

VDDCPU1 

PCICLK_F0 

PCICLK_F1 

8 

VDDPCI0 

PCICLK_F2 

14 

VDDPCI1 

66MHZ_OUT0/3V66_2 

66MHZ_OUT1/3V66_3 

66MHZ_OUT2/3V66_4 

39 

38 

35 

56 

52 

49 

45 

51 

48 

44 

10 

11 

12 

13 

16 

17 

18 

5 

6 

7 

21 

22 

23 

1 

0603 33 

1 

0603 33 

33/NA 0603 1 

33 0603 1 

33 0603 1 

33/NA 0603 1 

33 0603 1 

33 0603 1 

1 

0603 133 0603 133 0603 133 0603 133 0603 33 

1 

0603 33 

1 

0603 133 0603 33 

1 

0603 

2 R105 

2 R159 

2 R155 

2 R138 

2 R121 

2 R145 

2 R130 

2 R116 

2 R131 

2 R127 

2 R542 

2 R117 

2 R119 

2 R139 

2 R109 

2 R108 

2 R160 

GND 

33 

R140 1 2 0603D 0/NA 

R144 1 2 0603D 0/NA 

1 2 R154 

0603 49.9 1 1% 2 R129 

C137 C109 

0603 49.9 1 1% 2 R120 

10P/NA 10P/NA 

0603 49.9 1% 

0603 0603 

1 2 R137 

10% 10% 

0603 49.9 1 1% 2 R125 

0603 49.9 1 1% 2 R115 

0603 49.9 1% 

C120 C123 C116 C112 C547 

10P/NA 10P/NA 10P/NA 10P/NA 10P/NA 

0603 0603 0603 0603 0603 

10% 10% 10% 10% 10% 

GND 

14M_CODEC 12 

14M_ICH 9 

HCLK_CPU# 3 

HCLK_CPU 3 

HCLK_MCH# 5 

HCLK_MCH 5 

CLK_ITP_CPU# 3 

CLK_ITP_CPU 3 

C104 

10P/NA 

0603 

10% 

GND 

PCICLK_1394 15 

PCICLK_LPC 19 

PCICLK_MINIPCI 17 

PCICLK_CARD 18 

PCICLK_LAN 16 

PCICLK_ICH 9 

66M_MCH 5 

66M_ICH 10 

B 

3V66_0 

66MHZ_IN/3V66_5 

33 

24 


1 

2 

2 

1 

2 

CPU 

166.66 

100.00 

200.00 

Tristate 

Reserved 

Reserved 

1 

2 

1 

3V66[5:0] 

66.66 

66.66 

66.66 

Tristate 

Reserved 

Reserved 

PCI* 

33.33 

33.33 

33.33 

33.33 

Tristate 

TCLK/2 

Reserved 

Reserved 

UNIT: MHz 


1 

Sheet 4 of 29

5 

Maximum length less than 0.5" from pin to 

voltage divider. 

+VCCP (1.05V) 

R207 

49.9 

0603 

1% 

HAVREF HCCVREF 

5 

4 

4 

Less than 0.5" 

HXSWING HYSWING 

3 

R175 1 2 

R562 1 8.2K/NA 2 

R563 1 8.2K 2 

R568 1 8.2K 2 

R560 1 8.2K 2 

R558 1 8.2K 2 

D 

R565 1 8.2K 

R554 1 8.2K 

8.2K 

2 

2 

D 

C 

B 

HA#[3..31] 

3 HA#[3..31] 

HXRCOMP & HYRCOMP should be 


Less than 0.5" 

1 2 HXRCOMP 

R549 27.4 

1 2 HYRCOMP 

R566 27.4 

GND 

HREQ#[0..4] 

3 HREQ#[0..4] 

3 HADSTB#0 

3 HADSTB#1 

HDSTBP#[0..3] 

3 HDSTBP#[0..3] 

HDSTBN#[0..3] 

3 HDSTBN#[0..3] 

HDINV#[0..3] 

3 HDINV#[0..3] 

3 HADS# 

3 HTRDY# 

3 HDRDY# 

3 HDEFER# 

3 HHITM# 

3 HHIT# 

3 HLOCK# 

3 HBR0# 

3 HBNR# 

3 HBPRI# 

3 HDBSY# 

HRS#[0..2] 

3 HRS#[0..2] 

3,4 HCPURST# 

9,20 PWROK 

U502B 

HA#3 P23 

HA#4 

HA[3]# 

T25 

HA#5 

HA[4]# 

T28 

HA#6 

HA[5]# 

R27 

HA#7 

HA[6]# 

U23 

HA#8 

HA[7]# 

U24 

HA#9 

HA[8]# 

R24 

HA#10 

HA[9]# 

U28 

HA#11 

HA[10]# 

V28 

HA#12 

HA[11]# 

U27 

HA#13 

HA[12]# 

T27 

HA#14 

HA[13]# 

V27 

HA#15 

HA[14]# 

U25 

HA#16 

HA[15]# 

V26 

HA#17 

HA[16]# 

Y24 

HA#18 

HA[17]# 

V25 

HA#19 

HA[18]# 

V23 

HA#20 

HA[19]# 

W25 

HA#21 

HA[20]# 

Y25 

HA#22 

HA[21]# 

AA27 

HA#23 

HA[22]# 

W24 

HA#24 

HA[23]# 

W23 

HA#25 

HA[24]# 

W27 

HA#26 

HA[25]# 

Y27 

HA#27 

HA[26]# 

AA28 

HA#28 

HA[27]# 

W28 

HA#29 

HA[28]# 

AB27 

HA#30 

HA[29]# 

Y26 

HA#31 

HA[30]# 

AB28 

HA[31]# 

HREQ#0 R28 

HREQ#1 

HREQ[0]# 

P25 

HREQ#2 

HREQ[1]# 

R23 

HREQ#3 

HREQ[2]# 

R25 

HREQ#4 

HREQ[3]# 

T23 

HREQ[4]# 

T26 

HADSTB[0]# 

AA26 

HADSTB[1]# 

HXRCOMP B20 

HXSWING 

HXRCOMP 

B18 

HYRCOMP 

HXSWING 

H28 

HYSWING 

HYRCOMP 

K28 

HYSWING 

HDSTBP#0 K27 

HDSTBP#1 

HDSTBP[0]# 

D26 

HDSTBP#2 

HDSTBP[1]# 

E21 

HDSTBP#3 

HDSTBP[2]# 

E18 

HDSTBP[3]# 

HDSTBN#0 J28 

HDSTBN#1 

HDSTBN[0]# 

C27 

HDSTBN#2 

HDSTBN[1]# 

E22 

HDSTBN#3 

HDSTBN[2]# 

D18 

HDSTBN[3]# 

HDINV#0 J25 

HDINV#1 

DINV[0]# 

E25 

HDINV#2 

DINV[1]# 

B25 

HDINV#3 

DINV[2]# 

G19 

DINV[3]# 

L28 

ADS# 

M25 

HTRDY# 

N24 

DRDY# 

M28 

DEFER# 

N28 

HITM# 

N27 

HIT# 

P27 

HLOCK# 

M23 

BREQ0# 

N25 

BNR# 

P28 

BPRI# 

M26 

HRS#0 

DBSY# 

N23 

HRS#1 

RS[0]# 

P26 

HRS#2 

RS[1]# 

M27 

RS[2]# 

F15 

CPURST# 

1 2 J11 

R101 0/NA 

PWROK 

0603D_DFS MONTARA-GM 

BGA707_25 

HD[0]# 

HD[1]# 

HD[2]# 

HD[3]# 

HD[4]# 

HD[5]# 

HD[6]# 

HD[7]# 

HD[8]# 

HD[9]# 

HD[10]# 

HD[11]# 

HD[12]# 

HD[13]# 

HD[14]# 

HD[15]# 

HD[16]# 

HD[17]# 

HD18]# 

HD[19]# 

HD[20]# 

HD[21]# 

HD[22]# 

HD[23]# 

HD24]# 

HD[25]# 

HD[26]# 

HD[27]# 

HD[28]# 

HD[29]# 

HD[30]# 

HD[31]# 

HD[32]# 

HD[33]# 

HD[34]# 

HD[35]# 

HD[36]# 

HD[37]# 

HD[38]# 

HD[39]# 

HD[40]# 

HD[41]# 

HD[42]# 

HD[43]# 

HD[44]# 

HD[45]# 

HD[46]# 

HD[47]# 

HD[48]# 

HD[49]# 

HD[50]# 

HD[51]# 

HD[52]# 

HD[53]# 

HD[54]# 

HD[55]# 

HD[56]# 

HD[57]# 

HD[58]# 

HD[59]# 

HD[60]# 

HD[61]# 

HD[62]# 

HD[63]# 

HDVREF[0] 

HDVREF[1] 

HDVREF[2] 

HAVREF 

HCCVREF 

K22 

H27 

K25 

L24 

J27 

G28 

L27 

L23 

L25 

J24 

H25 

K23 

G27 

K26 

J23 

H26 

F25 

F26 

B27 

H23 

E27 

G25 

F28 

D27 

G24 

C28 

B26 

G22 

C26 

E26 

G23 

B28 

B21 

G21 

C24 

C23 

D22 

C25 

E24 

D24 

G20 

E23 

B22 

B23 

F23 

F21 

C20 

C21 

G18 

E19 

E20 

G17 

D20 

F19 

C19 

C17 

F17 

B19 

G16 

E16 

C16 

E17 

D16 

C18 

K21 

J21 

J17 

Y22 

Y28 

HD#0 

HD#1 

HD#2 

HD#3 

HD#4 

HD#5 

HD#6 

HD#7 

HD#8 

HD#9 

HD#10 

HD#11 

HD#12 

HD#13 

HD#14 

HD#15 

HD#16 

HD#17 

HD#18 

HD#19 

HD#20 

HD#21 

HD#22 

HD#23 

HD#24 

HD#25 

HD#26 

HD#27 

HD#28 

HD#29 

HD#30 

HD#31 

HD#32 

HD#33 

HD#34 

HD#35 

HD#36 

HD#37 

HD#38 

HD#39 

HD#40 

HD#41 

HD#42 

HD#43 

HD#44 

HD#45 

HD#46 

HD#47 

HD#48 

HD#49 

HD#50 

HD#51 

HD#52 

HD#53 

HD#54 

HD#55 

HD#56 

HD#57 

HD#58 

HD#59 

HD#60 

HD#61 

HD#62 

HD#63 

HAVREF 

HCCVREF 

HD#[0..63] 

HD#[0..63] 3 

R553 1 2 

E5 

+1.5V 

R564 1 330/NA2 

F5 

R555 1 330/NA2 

E3 

R557 1 330/NA2 

E2 

R567 1 330/NA2 

G5 

R707 

R561 1 330/NA2 

F4 

2.2K 

R559 1 330/NA2 

G6 

0603 

R176 1 330/NA2 

F6 

330 

PM_SUSCLK 

9 AGPBUSY# 

F7 

GND 

4 HCLK_MCH 

AE29 

4 HCLK_MCH# 

AD29 

PM_SUSCLK D5 

D Q517 

3,9 HDPSLP# 

Y23 

G S 

9 SUSCLK 

2N7002 

3 HDPWR# 

AA22 

4 48M_DREFCLK 

B7 

14 TXOUT0- 

G14 

GND 

14 TXOUT1- 

E15 

14 TXOUT2- 

C15 

1 2 

C13 

14 TXOUT0+ 

F14 

R546 0/NA 

14 TXOUT1+ 

E14 

14 TXOUT2+ 

C14 

B13 

14 TXOUT3- 

H12 

14 TXOUT4- 

E12 

14 TXOUT5- 

C12 

G11 

14 TXOUT3+ 

G12 

Place near to GMCH. 

14 TXOUT4+ 

E11 

14 TXOUT5+ 

C11 

G10 

DVOVREF 

14 TXCLKOUT0- 

D14 

C566 

14 TXCLKOUT0+ 

E13 

0.1U 

14 TXCLKOUT1- 

E10 

0603 

50V 

14 TXCLKOUT1+ 

F10 

R142 

+3V 

1 2 D6 

GND 

10K 

4 66M_MCH 

Y3 

8 DVOVREF 

F1 

HUB_HI[0..10] 

10 HUB_HI[0..10] 

HUB_HI0 U7 

HUB_HI1 U4 

HUB_HI2 U3 

HUB_HI3 V3 

HUB_HI4 W2 

HUB_HI5 W6 

HUB_HI6 V6 

HUB_HI7 W7 

HUB_HI8 T3 

HUB_HI9 V5 

HUB_HI10 V4 

+VCCP 

10 HUB_STB 

W3 

10 HUB_STB# 

V2 

R190 Maximum length less than 

HUB_MCH_VREF W1 

49.9 

HUB_RCOMP 

0.5" from pin to voltage 

T2 

0603 

1% divider. 

9 MCH_PCIRST# 

AD28 

REFSET E8 

C158 C159 C157 R191 

0.1U 0.1U 1U 100 

G9 

0603 0603 0603 0603 

14 CRT_DDDA 

B6 

50V 50V 

1% 

14 CRT_DDCK 

+3V 

1 2 B4 

1R135 10K2 

C5 

R143 10K 

GND 

14 CRT_R 

A7 

A8 

14 CRT_G 

C8 

D8 

14 CRT_B 

C9 

GND 

D9 

14 CRT_HSYNC 

H10 

14 CRT_VSYNC 

J9 

4 66M_DEFSSCLK 

B17 

U502A 

ADDID[0] 

ADDID[1] 

ADDID[2] 

ADDID[3] 

ADDID[4] 

ADDID[5] 

ADDID[6] 

ADDID[7] 

AGPBUSY# 

BCLK 

BCLK# 

DPMS 

DPSLP# 

DPWR# 

DREFCLK 

IYAM[0] 

IYAM[1] 

IYAM[2] 

IYAM[3] 

IYAP[0] 

IYAP[1] 

IYAP[2] 

IYAP[3] 

IYBM[0] 

IYBM[1] 

IYBM[2] 

IYBM[3] 

IYBP[0] 

IYBP[1] 

IYBP[2] 

IYBP[3] 

ICLKAM 

ICLKAP 

ICLKBM 

ICLKBP 

EXTTS_0 

GCLKIN 

GVREF 

HL[0] 

HL[1] 

HL[2] 

HL[3] 

HL[4] 

HL[5] 

HL[6] 

HL[7] 

HL[8] 

HL[9] 

HL[10] 

HLSTB 

HLSTB# 

HLVREF 

HLRCOMP 

RSTIN# 

REFSET 

DDCADATE 

DDCACLK 

DDCPCLK 

DDCPDATA 

RED 

RED# 

GEEN 

GREEN# 

BLUE 

BLUE# 

HSYNC 

VSYNC 

DEFSSCLK 

DVOBCLK 

DVOBCLK# 

DVOBD[0] 

DVOBD[1] 

DVOBD[2] 

DVOBD[3] 

DVOBD[4] 

DVOBD[5] 

DVOBD[6] 

DVOBD[7] 

DVOBD[8] 

DVOBD[9] 

DVOBD[10] 

DVOBD[11] 

DVOBCCLKINT 

DVOBCINTR# 

DVOBFLDSTL 

DVOBBLANK# 

DVOBHSYNC 

DVOBVSYNC 

DVOCCLK 

DVOCCLK# 

DVOCD[0] 

DVOCD[1] 

DVOCD[2] 

DVOCD[3] 

DVOCD[4] 

DVOCD[5] 

DVOCD[6] 

DVOCD[7] 

DVOCD[8] 

DVOCD[9] 

DVOCD[10] 

DVOCD[11] 

DVODETECT 

DVORCOMP 

DVOCFLDSTL 

DVOCBLANK# 

DVOCHSYNC 

DVOCVSYNC 

LCLKCTLA 

LCLKCTLB 

LIBG 

MDDCCLK 

MDDCDATA 

MDVICLK 

MDVIDATA 

MI2CCLK 

MI2CDATA 

PANELBKLTCTL 

PANELBKLTEN 

PANELVDDEN 

PSWING 

RCVENIN# 

RCVENOUT# 

NC_0 

NC_1 

NC_2 

NC_3 

NC_4 

NC_5 

NC_6 

NC_7 

NC_8 

NC_9 

NC_10 

NC_11 

P3 

P4 

R3 

R5 

R6 

R4 

P6 

P5 

N5 

P2 

N2 

N3 

M1 

M5 

M3 

POUT/DET# 8 

G2 

DVOBCINTR# 8 

M2 1 2 

GND 

L2 R569 

100K/NA 

T6 0603 

T5 

J3 

DVOCCLK 8 

J2 

DVOCCLK# 8 

K5 DVOCD0 

K1 DVOCD1 DVOCD[0..11] 

K3 DVOCD2 

DVOCD[0..11] 8 

K2 DVOCD3 

J6 DVOCD4 

J5 DVOCD5 

H2 DVOCD6 

H1 DVOCD7 

H3 DVOCD8 

H4 DVOCD9 

H6 DVOCD10 

G3 DVOCD11 

L7 1 2 

D1 1R187 33 2 

GND 

H5 R556 40.2 

DVOCFLDSTL 8 

L3 1 2 

R5700/NA 

K6 

DVOCHSYNC 8 

L5 

R179 

DVOCVSYNC 8 

100K/NA 

R133 10K/NA 

0603 

H9 1 2 

+3V 

C6 1 2 

R134 10K/NA 

A10 R540 1 2 

GND 

1.5K 

GND 

P7 1 2 

+1.5V 

T7 1R201 10K2 

N7 1R203 10K2 

+1.5V 

M6 1R197 10K2 

K7 R198 10K 

MI2CCLK 8 

N6 

MI2CDATA 8 

G8 1 2 

BLADJ 20,21 

F8 R1830/NA 

ENBL 21 

A5 

FPVCC 14 

U2 MCH_PSWING 

AC16 RCVENIN# 1 2 

AC15 RCVENOUT# R209 0/NA 

AJ29 

AH29 

B29 

A29 

AJ28 

A28 

AA9 

AJ4 

AJ2 

A2 

AH1 

B1 

C 

B 

A C189 C190 R208 

C580 C577 R586 

C563 R548 

C568 R571 

GND 

A 

0.1U 1U 100 

0.1U 1U 100 

0.1U 150 

0.1U 150 

0603 0603 0603 

0603 0603 0603 

0603 0603 

0603 0603 

GND 

50V 

1% 

50V 

1% 

50V 

50V 

1 

2 

1 

2 

1 

2 

1 

2 

GND 

1 

2 

1 

2 

+VCCP 

1 

2 

1 

2 

R585 

49.9 

0603 

1% 

GND 

1 

2 

+VCCP +VCCP 


1 

2 

1 

2 

1 

2 

R547 

301 

0603 

GND 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

GND 

1 

2 

D 

S 

R572 

301 

0603 

3 

+1.5V 

Non SSC 

W/ SSC 

+1.2V 

1 

2 

1 

2 

+1.2V 

R583 

243 

0603 

1% 

R582 

100 

0603 

1% 

ADD ID : 0x7Fh 

1 

2 

R573 

1 2 

27.4 

0603 

C579 

0.1U 

0603 

50V 

1 

2 

HUB_RCOMP 

HUB_MCH_VREF 

C578 

0.01U 

0603 

1 2 

R550 0/NA 

0603D_DFS 

2 

MONTARA-GM 

BGA707_25 

MCH_PSWING 

2 

1 

2 

C573 

0.1U 

0603 

50V 

1 

2 

+1.2V 

1 

2 

1 

C574 

1U 

0603 

2 

R577 

49.9 

0603 

1% 

R576 

100 

0603 

1% 

Title 

Size 

C 

REFSET 

Document 

Number 

R177 

1 2 

137 

0603 

1% 

1 

1 

2 


GND 

Rev 

411675300001 03 


1 

Sheet 5 of 29

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

Place within 0.5" with 15-mil wide. 

Clock config bit GST[1,0] 

PSB/Sys Mem Core/GFX Core(CL/CH) 

00(def): 400/266/200(133/200) 

01 : 400/200/200(100/200) 

10 : 400/200/133(100/133) 

411675300001 03 


C 

6 29 


Title 

Size 

Document 

Number 

Rev 


NB_MD0 

NB_MD1 

NB_MD2 

NB_MD3 

NB_MD4 

NB_MD5 

NB_MD6 

NB_MD7 

NB_MD8 

NB_MD9 

NB_MD10 

NB_MD11 

NB_MD12 

NB_MD13 

NB_MD14 

NB_MD15 

NB_MD26 

NB_MD23 

NB_MD18 

NB_MD29 

NB_MD28 

NB_MD24 

NB_MD17 

NB_MD19 

NB_MD30 

NB_MD22 

NB_MD21 

NB_MD16 

NB_MD27 

NB_MD25 

NB_MD31 

NB_MD20 

NB_MD53 

NB_MD42 

NB_MD59 

NB_MD51 

NB_MD50 

NB_MD39 

NB_MD34 

NB_MD61 

NB_MD57 

NB_MD45 

NB_MD44 

NB_MD48 

NB_MD40 

NB_MD33 

NB_MD58 

NB_MD56 

NB_MD35 

NB_MD63 

NB_MD46 

NB_MD52 

NB_MD38 

NB_MD37 

NB_MD55 

NB_MD32 

NB_MD62 

NB_MD43 

NB_MD41 

NB_MD49 

NB_MD47 

NB_MD60 

NB_MD36 

NB_MD54 

NB_MD[0..63] 

NB_CB7 

NB_CB6 

NB_CB5 

NB_CB4 

NB_CB3 

NB_CB2 

NB_CB1 

NB_CB0 

NB_CB[0..7] 

NB_DQS0 

NB_DQS1 

NB_DQS2 

NB_DQS3 

NB_DQS7 

NB_DQS4 

NB_DQS5 

NB_DQS6 

NB_DM3 

NB_DM4 

NB_DM6 

NB_DM5 

NB_DM0 

NB_DM1 

NB_DM2 

NB_DM7 

NB_DM8 

NB_DQS[0..7] 

NB_DM[0..8] 

NB_MA0 

SMA1 

SMA2 

NB_MA3 

SMA5 

SMA4 

NB_MA6 

NB_MA11 

NB_MA10 

NB_MA9 

NB_MA8 

NB_MA7 

NB_MA12 

NB_MA[6..12] 

SMAB1 

SMAB2 

SMAB4 

SMAB5 

SMAB[1..2] 

SMAB[4..5] 

MCH_SMVSWINGH 

MCH_SMVSWINGL 

MCH_SMVSWINGL 

MCH_SMVSWINGH 

MCH_SMRCOMP 

MCH_SMRCOMP 

VTTHF_0 

VTTHF_1 

VTTHF_2 

VTTHF_3 

VTTHF_4 

VTTHF_0 

VTTHF_1 

VTTHF_2 

VTTHF_3 

VTTHF_4 

VCCASM 

VCCGPIO 

VCCQSM 

VCCADPLLA 

VCCADPLLB 

VCCAGPLL 

VCCAHPLL 

VCCAHPLL VCCAGPLL 

VSSADAC 

VCCASM 

VCCGPIO 

VCCQSM 

VCCADPLLA 

VCCADPLLB 

VSSADAC 

VCCADAC 

VCCTXLVDS 

VCCTXLVDS 

VCCALVDS 

VCCADAC 

GST0 

GST1 

GST1 

GST0 

NB_DQS8 

SMA[1..2] 

SMA[4..5] 

NB_MA0 

NB_MA3 

GND GND 

+2.5V_DDR +2.5V_DDR 

GND 

GND 

GND 

+1.25V_DDR 

+2.5V_DDR 

GND 

GND 

+1.2V 

GND 

GND 

GND GND 

+1.2V 

+1.2V 

GND 

+1.5V 

GND 

GND 

GND 

+1.5V 

GND 

+1.2V 

GND 

+3V 

GND 

+2.5V_DDR 

GND 

+1.2V +1.2V 

GND 

+2.5V_DDR 

GND 

GND 

GND 

GND 

GND 

GND 

+VCCP 

+1.2V 

+1.5V 

+1.5V 

+2.5V_DDR 

+1.5V +1.5V 

C586 

0.01U 

0603 

1 

2 

C162 

10U 

10V 

1206 

1 

2 

C209 

10U 

10V 

1206 

1 

2 

L512 

120Z/100M 

1 2 

C171 

0.1U 

50V 

0603 

1 

2 

R587 

60.4 

0603 

1% 

1 

2 

L515 

120Z/100M 

1 2 

C583 

0.1U 

50V 

0603 

1 

2 

U502C 

MONTARA-GM 

BGA707_25 

F12 

D12 

B12 

AA5 

L4 

C4 

F3 

D3 

C3 

B3 

F2 

D2 

C2 

B2 

D7 

AD22 

AD20 

AC24 

AB2 

AA2 

AC26 

AB25 

AC3 

AD4 

AC2 

AD2 

AB23 

AB24 

AA3 

AB4 

AC7 

AB7 

AC9 

AC10 

AD23 

AD26 

AC22 

AC25 

AF2 

AE3 

AF4 

AH2 

AD3 

AE2 

AG4 

AH3 

AD6 

AG5 

AG7 

AF5 

AE8 

AH4 

AF7 

AH6 

AF8 

AG8 

AH9 

AG10 

AH7 

AD9 

AF10 

AE11 

AH10 

AH11 

AG13 

AF14 

AG11 

AD12 

AF13 

AH13 

AH16 

AG17 

AF19 

AE20 

AD18 

AE18 

AH18 

AG19 

AH20 

AG20 

AF22 

AH22 

AF20 

AH19 

AH21 

AG22 

AE23 

AH23 

AE24 

AH25 

AG23 

AF23 

AF25 

AG25 

AH26 

AE26 

AF28 

AG28 

AG26 

AF26 

AE27 

AD27 

AG14 

AE14 

AE17 

AG16 

AH14 

AE15 

AF16 

AF17 

AG2 

AH5 

AH8 

AE12 

AH17 

AE21 

AH24 

AH27 

AD15 

AC18 

AD14 

AD13 

AD17 

AD11 

AC13 

AD8 

AD7 

AC6 

AC5 

AC19 

AD5 

AB5 

AD16 

AC12 

AF11 

AD10 

AB1 

AJ24 

AJ19 

AJ22 

AC21 

AD25 

AE5 

AE6 

AE9 

AH12 

AD19 

AD21 

AD24 

AH28 

AH15 

RSVD_0 

RSVD_1 

RSVD_2 

RSVD_3 

RSVD_4 

RSVD_5 

RSVD_6 

RSVD_7 

RSVD_8 

RSVD_9 

RSVD_10 

RSVD_11 

RSVD_12 

RSVD_13 

RSVD_14 

SBA[0] 

SBA[1] 

SCAS# 

SCK[0] 

SCK[0]# 

SCK[1] 

SCK[1]# 

SCK[2] 

SCK[2]# 

SCK[3] 

SCK[3]# 

SCK[4] 

SCK[4]# 

SCK[5] 

SCK[5]# 

SCKE[0] 

SCKE[1] 

SCKE[2] 

SCKE[3] 

SCS[0]# 

SCS[1]# 

SCS[2]# 

SCS[3]# 

SDQ[0] 

SDQ[1] 

SDQ[2] 

SDQ[3] 

SDQ[4] 

SDQ[5] 

SDQ[6] 

SDQ[7] 

SDQ[8] 

SDQ[9] 

SDQ[10] 

SDQ[12] 

SDQ[11] 

SDQ[13] 

SDQ[14] 

SDQ[15] 

SDQ[16] 

SDQ[17] 

SDQ[18] 

SDQ[19] 

SDQ[20] 

SDQ[21] 

SDQ[22] 

SDQ[23] 

SDQ[24] 

SDQ[25] 

SDQ[26] 

SDQ[27] 

SDQ[28] 

SDQ[29] 

SDQ[30] 

SDQ[31] 

SDQ[32] 

SDQ[33] 

SDQ[34] 

SDQ[35] 

SDQ[36] 

SDQ[37] 

SDQ[38] 

SDQ[39] 

SDQ[40] 

SDQ[41] 

SDQ[42] 

SDQ[43] 

SDQ[44] 

SDQ[45] 

SDQ[46] 

SDQ[47] 

SDQ[48] 

SDQ[49] 

SDQ[50] 

SDQ[51] 

SDQ[52] 

SDQ[53] 

SDQ[54] 

SDQ[55] 

SDQ[56] 

SDQ[57] 

SDQ[59] 

SDQ[58] 

SDQ[60] 

SDQ[61] 

SDQ[62] 

SDQ[63] 

SDQ[64] 

SDQ[65] 

SDQ[66] 

SDQ[67] 

SDQ[68] 

SDQ[69] 

SDQ[70] 

SDQ[71] 

SDQS[0] 

SDQS[1] 

SDQS[2] 

SDQS[3] 

SDQS[4] 

SDQS[5] 

SDQS[6] 

SDQS[7] 

SDQS[8] 

SMA[0] 

SMA[1] 

SMA[2] 

SMA[3] 

SMA[4] 

SMA[5] 

SMA[6] 

SMA[7] 

SMA[8] 

SMA[9] 

SMA[10] 

SMA[11] 

SMA[12] 

SMAB[1] 

SMAB[2] 

SMAB[4] 

SMAB[5] 

SMRCOMP 

SMVREF_0 

SMVSWINGH 

SMVSWINGL 

SRAS# 

SWE# 

SDM[0] 

SDM[1] 

SDM[2] 

SDM[3] 

SDM[4] 

SDM[5] 

SDM[6] 

SDM[7] 

SDM[8] 

C193 

10U 

10V 

1206 

1 

2 

C127 

10U 

10V 

1206 

1 

2 

C170 

0.1U 

50V 

0603 

1 

2 

C540 

22U 

10V 

1206 

1 

2 

C569 

0.1U 

50V 

0603 

1 

2 

C146 

0.1U 

50V 

0603 

1 

2 

L516 

120Z/100M 

1 2 

C177 

0.1U 

50V 

0603 

1 

2 

C554 0.1U 

1 2 

L521 

120Z/100M 

1 2 

L15 

120Z/100M 

1 2 

L522 

120Z/100M 

1 2 

C200 

0.1U 

50V 

0603 

1 

2 

L524 

120Z/100M 

1 2 

U502D 

MONTARA-GM 

BGA707_25 

W21 

AA19 

AA17 

T17 

P17 

U16 

R16 

N16 

AA15 

T15 

P15 

J15 

U14 

R14 

N14 

H14 

T13 

P13 

B15 

B14 

J13 

G13 

P9 

M9 

K9 

R8 

N8 

M8 

L8 

J8 

H7 

E6 

M4 

J4 

E4 

N1 

J1 

E1 

V9 

W8 

U8 

V7 

U6 

W5 

Y1 

V1 

AJ8 

AJ6 

A4 

A3 

AG29 

AF29 

AC29 

AF27 

AJ25 

AF24 

AB22 

AJ21 

AF21 

AB20 

AF18 

AB18 

AJ17 

AB16 

AF15 

AB14 

AJ13 

AA13 

AF12 

AB12 

AA11 

AB10 

AJ9 

AF9 

Y9 

AB8 

AA8 

Y7 

AF6 

AB6 

AA6 

AJ5 

Y4 

AF3 

AB3 

AG1 

AC1 

A12 

D10 

B10 

F9 

B8 

B11 

AB29 

Y29 

K29 

F29 

A26 

V22 

T22 

P22 

M22 

H22 

U21 

R21 

N21 

L21 

H20 

A20 

J19 

H18 

A18 

H16 

G15 

V29 

M29 

H29 

A24 

A22 

B9 

A9 

A6 

B16 

Y2 

D29 

A11 

AF1 

AD1 

VCC_0 

VCC_1 

VCC_2 

VCC_3 

VCC_4 

VCC_5 

VCC_6 

VCC_7 

VCC_8 

VCC_9 

VCC_10 

VCC_11 

VCC_12 

VCC_13 

VCC_14 

VCC_15 

VCC_16 

VCC_17 

VCCDLVDS_0 

VCCDLVDS_1 

VCCDLVDS_2 

VCCDLVDS_3 

VCCDVO_0 

VCCDVO_1 

VCCDVO_2 

VCCDVO_3 

VCCDVO_4 

VCCDVO_5 

VCCDVO_6 

VCCDVO_7 

VCCDVO_8 

VCCDVO_9 

VCCDVO_10 

VCCDVO_11 

VCCDVO_12 

VCCDVO_13 

VCCDVO_14 

VCCDVO_15 

VCCHL_0 

VCCHL_1 

VCCHL_2 

VCCHL_3 

VCCHL_4 

VCCHL_5 

VCCHL_6 

VCCHL_7 

VCCQSM_0 

VCCQSM_1 

VCCGPIO_0 

VCCGPIO_1 

VCCSM_0 

VCCSM_1 

VCCSM_2 

VCCSM_3 

VCCSM_4 

VCCSM_5 

VCCSM_6 

VCCSM_7 

VCCSM_8 

VCCSM_9 

VCCSM_10 

VCCSM_11 

VCCSM_12 

VCCSM_13 

VCCSM_14 

VCCSM_15 

VCCSM_16 

VCCSM_17 

VCCSM_18 

VCCSM_19 

VCCSM_20 

VCCSM_21 

VCCSM_22 

VCCSM_23 

VCCSM_24 

VCCSM_25 

VCCSM_26 

VCCSM_27 

VCCSM_28 

VCCSM_29 

VCCSM_30 

VCCSM_31 

VCCSM_32 

VCCSM_33 

VCCSM_34 

VCCSM_35 

VCCSM_36 

VCCTXLVDS_0 

VCCTXLVDS_1 

VCCTXLVDS_2 

VCCTXLVDS_3 

VSSADAC 

VSSALVDS 

VTTLF_0 

VTTLF_1 

VTTLF_2 

VTTLF_3 

VTTLF_4 

VTTLF_5 

VTTLF_6 

VTTLF_7 

VTTLF_8 

VTTLF_9 

VTTLF_10 

VTTLF_11 

VTTLF_12 

VTTLF_13 

VTTLF_14 

VTTLF_15 

VTTLF_16 

VTTLF_17 

VTTLF_18 

VTTLF_19 

VTTLF_20 

VTTHF_0 

VTTHF_1 

VTTHF_2 

VTTHF_3 

VTTHF_4 

VCCADAC_0 

VCCADAC_1 

VCCADPLLA 

VCCADPLLB 

VCCAGPLL 

VCCAHPLL 

VCCALVDS 

VCCASM_0 

VCCASM_1 

R594 

150 

0603 

1 

2 

C555 

0.01U 

0603 

1 

2 

C557 

0.01U 

0603 

1 

2 

C161 

10U 

10V 

1206 

1 

2 

C205 

0.1U 

50V 

0603 

1 

2 

C559 

22U 

10V 

1206 

1 

2 

C176 

0.1U 

50V 

0603 

1 

2 

R167 

1K/NA 

0603 

1 

2 

C214 

10U 

10V 

1206 

1 

2 

R588 

60.4 

0603 

1% 

1 

2 

C180 

0.1U 

50V 

0603 

1 

2 

C131 

22U 

10V 

1206 

1 

2 

C565 

0.1U 

50V 

0603 

1 

2 

C594 

0.1U 

50V 

0603 

1 

2 

C585 

0.1U/NA 

50V 

0603 

1 

2 

C178 

0.1U 

50V 

0603 

1 

2 

C541 

10U 

10V 

1206 

1 

2 

C590 

22U 

10V 

1206 

1 

2 

C173 

0.1U 

50V 

0603 

1 

2 

C181 

0.1U 

50V 

0603 

1 

2 

C591 

4.7U 

0805 

+80-20% 

1 

2 

L519 

120Z/100M 

1 2 

C544 0.1U 

1 2 

C551 

0.01U 

0603 

1 

2 

C552 

10U 

10V 

1206 

1 

2 

U502E 

MONTARA-GM 

BGA707_25 

AA29 

W29 

U29 

N29 

L29 

J29 

G29 

E29 

C29 

AE28 

AC28 

E28 

D28 

AJ27 

AG27 

AC27 

F27 

A27 

AJ26 

AB26 

W26 

R26 

N26 

L26 

J26 

G26 

AE25 

AA25 

D25 

A25 

AG24 

AA24 

V24 

T24 

P24 

M24 

K24 

H24 

F24 

B24 

AJ23 

AC23 

AA23 

D23 

A23 

AE22 

W22 

U22 

R22 

N22 

L22 

J22 

F22 

C22 

AG21 

AB21 

AA21 

Y21 

V21 

T21 

P21 

M21 

H21 

D21 

A21 

AJ20 

AC20 

AA20 

J20 

F20 

AE19 

AB19 

H19 

D19 

A19 

AJ18 

AG18 

AA18 

J18 

F18 

AC17 

AB17 

U17 

R17 

N17 

H17 

D17 

A17 

AE16 

AA16 

T16 

P16 

J16 

F16 

AG15 

AB15 

U15 

R15 

N15 

H15 

D15 

AC14 

AA14 

T14 

P14 

J14 

AE13 

AB13 

U13 

R13 

N13 

H13 

F13 

D13 

A13 

AJ12 

AG12 

AA12 

J12 

AJ11 

AC11 

AB11 

H11 

F11 

D11 

AE10 

AJ10 

AA10 

C10 

AG9 

AB9 

W9 

U9 

T9 

R9 

N9 

L9 

E9 

AC8 

Y8 

V8 

T8 

P8 

K8 

H8 

AJ7 

AE7 

AA7 

R7 

M7 

J7 

G7 

E7 

C7 

AG6 

Y6 

L6 

Y5 

U5 

B5 

AE4 

AC4 

AA4 

W4 

T4 

N4 

K4 

G4 

D4 

AJ3 

AG3 

R2 

AJ1 

AE1 

AA1 

U1 

L1 

G1 

C1 

J10 

U26 

VSS_0 

VSS_1 

VSS_2 

VSS_3 

VSS_4 

VSS_5 

VSS_6 

VSS_7 

VSS_8 

VSS_9 

VSS_10 

VSS_11 

VSS_12 

VSS_13 

VSS_14 

VSS_15 

VSS_16 

VSS_17 

VSS_18 

VSS_19 

VSS_20 

VSS_21 

VSS_22 

VSS_23 

VSS_24 

VSS_25 

VSS_26 

VSS_27 

VSS_28 

VSS_29 

VSS_30 

VSS_31 

VSS_32 

VSS_33 

VSS_34 

VSS_35 

VSS_36 

VSS_37 

VSS_38 

VSS_39 

VSS_40 

VSS_41 

VSS_42 

VSS_43 

VSS_44 

VSS_45 

VSS_46 

VSS_47 

VSS_48 

VSS_49 

VSS_50 

VSS_51 

VSS_52 

VSS_53 

VSS_54 

VSS_55 

VSS_56 

VSS_57 

VSS_58 

VSS_59 

VSS_60 

VSS_61 

VSS_62 

VSS_63 

VSS_64 

VSS_65 

VSS_66 

VSS_67 

VSS_68 

VSS_69 

VSS_70 

VSS_71 

VSS_72 

VSS_73 

VSS_74 

VSS_75 

VSS_76 

VSS_77 

VSS_78 

VSS_79 

VSS_80 

VSS_81 

VSS_82 

VSS_83 

VSS_84 

VSS_85 

VSS_86 

VSS_87 

VSS_88 

VSS_89 

VSS_90 

VSS_91 

VSS_92 

VSS_93 

VSS_94 

VSS_95 

VSS_96 

VSS_97 

VSS_98 

VSS_99 

VSS_100 

VSS_101 

VSS_102 

VSS_103 

VSS_104 

VSS_105 

VSS_106 

VSS_107 

VSS_108 

VSS_109 

VSS_110 

VSS_111 

VSS_112 

VSS_113 

VSS_114 

VSS_115 

VSS_116 

VSS_117 

VSS_118 

VSS_119 

VSS_120 

VSS_121 

VSS_122 

VSS_123 

VSS_124 

VSS_125 

VSS_126 

VSS_127 

VSS_128 

VSS_129 

VSS_130 

VSS_131 

VSS_132 

VSS_133 

VSS_134 

VSS_135 

VSS_136 

VSS_137 

VSS_138 

VSS_139 

VSS_140 

VSS_141 

VSS_142 

VSS_143 

VSS_144 

VSS_145 

VSS_146 

VSS_147 

VSS_148 

VSS_149 

VSS_150 

VSS_151 

VSS_152 

VSS_153 

VSS_154 

VSS_155 

VSS_156 

VSS_157 

VSS_158 

VSS_159 

VSS_160 

VSS_161 

VSS_162 

VSS_163 

VSS_164 

VSS_165 

VSS_166 

VSS_167 

VSS_168 

VSS_169 

VSS_170 

VSS_171 

VSS_172 

VSS_173 

VSS_174 

VSS_175 

VSS_176 

VSS_177 

VSS_178 

VSS_179 

VSS_180 

R164 

1K 

0603 

1 

2 

C560 

0.1U 

50V 

0603 

1 

2 

R597 

150 

0603 

1 

2 

L514 

120Z/100M 

1 2 

C211 

0.1U 

50V 

0603 

1 

2 

C192 

0.1U 

50V 

0603 

1 

2 

C582 

0.1U 

50V 

0603 

1 

2 

C571 0.1U 

1 2 

C194 

0.1U 

50V 

0603 

1 

2 

C550 

0.01U 

0603 

1 

2 

R596 

604 

0603 

1% 

1 

2 

C121 

0.01U 

0603 

1 

2 

TP15 

1 

C575 0.1U 

1 2 

C584 

0.1U 

50V 

0603 

1 

2 

C588 

10U 

10V 

1206 

1 

2 

C596 

0.1U 

50V 

0603 

1 

2 

C587 

0.1U 

50V 

0603 

1 

2 

C213 

10U 

10V 

1206 

1 

2 

C172 

10U 

10V 

1206 

1 

2 

C143 

0.1U 

50V 

0603 

1 

2 

C558 

0.01U 

0603 

1 

2 

C191 

0.1U 

50V 

0603 

1 

2 

C595 

0.1U 

50V 

0603 

1 

2 

C204 

0.1U 

50V 

0603 

1 

2 

L520 

120Z/100M 

1 2 

C561 

0.1U 

50V 

0603 

1 

2 

C155 

22U 

10V 

1206 

1 

2 

C593 

22U 

10V 

1206 

1 

2 

C592 

0.01U 

0603 

1 

2 

C567 0.1U 

1 2 

C556 

0.1U 

50V 

0603 

1 

2 

C545 

22U 

10V 

1206 

1 

2 

C212 

0.1U 

50V 

0603 

1 

2 

R595 

604 

0603 

1% 

1 

2 

NB_MD[0..63] 7 

NB_CB[0..7] 7 

NB_DQS[0..7] 7 

NB_DM[0..8] 7 

NB_MA[0..12] 

7 

SMAB[1..2] 

7 

SMAB[4..5] 

7 

NB_WE# 

7 

NB_CAS# 

7 

NB_RAS# 

7 

NB_BA1 

7 

NB_BA0 

7 

CS#0 

7 

CS#1 

7 

CS#2 

7 

CS#3 

7 

CKE3 

7 

CKE1 

7 

CKE2 

7 

CKE0 

7 

CLK_DDR0 

7 

CLK_DDR0# 

7 

CLK_DDR1 

7 

CLK_DDR1# 

7 

CLK_DDR2 

7 

CLK_DDR2# 

7 

CLK_DDR3 

7 

CLK_DDR4 

7 

CLK_DDR3# 

7 

CLK_DDR4# 

7 

CLK_DDR5 

7 

CLK_DDR5# 

7 

SMA[1..2] 

7 

SMA[4..5] 

7 

NB_MA0 

7 

NB_MA3 

7 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

411675300001 03 


C 

7 29 


Title 

Size 

Document 

Number 

Rev 


MD63 

MD45 

CLK_DDR4# 

MD25 

MA8 

MD30 

SMBDATA 

CLK_DDR3# 

MD20 

CAS# 

MD57 

CKE2 

MD5 

MD17 

MD61 

DQS7 

BA1 

MD4 

MD52 

MD31 

DQS8 

DQS1 

DM3 

MD18 

CLK_DDR3# 

NB_DM[0..8] 

BA1 

MD36 

CS#1 

MCB4 

MA12 

MCB5 

WE# 

MD49 

MD45 

CLK_DDR2 

MD52 

MCB6 

MD35 

DM8 

CKE0 

DM4 

MCB6 

CKE2 

MD20 

MA10 

MCB0 

NB_DQS[0..7] 

MD28 

MD21 

MD38 

SMAB[1..2] 

CLK_DDR1# 

NB_BA1 

DM8 

MD8 

MA9 

DM7 

MD11 

MD4 

MD12 

CLK_DDR3 

MA11 

MD7 

DQS3 

CKE3 

CLK_DDR1 

RAS# 

MD53 

SMAB[4..5] 

MD26 

MD56 

CLK_DDR3 

MD39 

MD6 

DQS6 

DQS2 

NB_CAS# 

DM6 

NB_MD[0..63] 

CAS# 

MA3 

CLK_DDR4 

DQS4 

MD38 

DM7 

CLK_DDR0# 

CLK_DDR5 

MCB7 

MD44 

DM1 

MD54 

MD29 

CLK_DDR1# 

MCB7 

SMA4 

MD0 

SMBCLK 

MA0 

MA0 

MD21 

MA6 

CKE0 

SMAB5 

MD30 

CKE1 

MD59 

MD10 

NB_WE# 

DM2 

MD13 

MD15 MD14 

MD36 

MD13 

MD44 

MD19 

MD46 

CS#3 

NB_CB[0..7] 

CKE3 

MD50 

MD53 

CLK_DDR5 

MD3 

MD23 

MD60 

DQS0 

MD58 

MD5 

CS#2 

MD23 

MD9 

MD32 

DM0 

MD47 

MD62 

SMAB4 

MD31 

DM6 

BA0 

CLK_DDR5# 

DM5 

MD33 

RAS# 

MD43 

MD40 

MD24 

MD15 

MD16 

SMA2 

DM2 

MD37 

MCB4 

MD2 

MD42 

MD28 

DM1 

CS#3 

MD60 

DM4 

MD22 

CS#1 

MA7 MA6 

CLK_DDR2# 

MD22 

DQS5 

MD41 

MD37 

MD51 

CLK_DDR5# 

MD63 

MD47 

MD61 

DM0 

MD48 

DM3 

CLK_DDR4 

MD55 

SMAB2 

NB_RAS# 

NB_BA0 

MCB3 

SMAB1 

MCB2 

MD46 

MD29 

MD12 

MD1 

MD54 

DM5 

MD55 

CLK_DDR4# 

CLK_DDR1 

MD14 

MD62 

CS#2 

MCB5 

CLK_DDR0 

MD39 

MD7 

MD6 

NB_MA[6..12] 

MCB1 

CS#0 

MD34 

MD27 

MA11 

MA8 

CKE1 

NB_MD18 

MD5 

NB_MA0 

NB_MD39 

MD50 

NB_DQS6 

BA0 

MD48 

NB_MD63 

NB_MD54 

CKE3 

MCB5 

NB_DM2 

NB_DM5 

NB_MD36 

NB_MD60 

NB_MA12 

MD4 

MD2 

NB_MD10 

MD59 

NB_MA8 

MD41 

MCB2 

DM2 

DQS5 

NB_MD14 

NB_MD23 

CKE2 

NB_MD21 

NB_MD53 

NB_MA10 

MD53 

NB_MD37 

CAS# 

NB_BA0 

MD26 

NB_MA3 

DM7 

NB_MD31 

NB_MD17 

NB_MD61 

MD28 

WE# 

NB_MD50 

MD62 

MD44 

NB_CB1 

NB_MD62 

CS#2 

CKE0 

NB_MD0 

MD49 

MA12 

NB_MD28 

MD1 

MD58 

MD51 

MD23 

NB_MD22 

CS#1 

DQS2 

DM5 

DM3 

MD45 

NB_DQS7 

DM6 

NB_DM8 

NB_MD24 

NB_MD47 

MA6 

MD24 

NB_DQS1 

NB_DM7 

NB_MD3 

NB_MD57 

NB_MD44 

MA8 

NB_MD15 

MD29 

SMAB5 

NB_RAS# 

MD56 

NB_WE# 

MA7 

CS#3 

MD54 

NB_MD40 

NB_MA7 

DQS0 

SMAB1 

NB_CAS# 

NB_MD56 

NB_MD51 

NB_DM1 

NB_MD35 

NB_MD20 

NB_MD49 

MD52 

MD39 

NB_MA9 

NB_DQS5 

NB_MD41 

NB_MD6 

DM8 

BA1 

DQS6 

NB_CB0 

NB_MD7 

NB_CB6 

NB_MA6 

MD31 

NB_CB5 

RAS# 

MD22 

NB_MD32 

NB_DM6 

NB_MD27 

MCB6 

NB_MD12 

MA3 

NB_MD58 

MCB1 

NB_MD5 

NB_MD45 

MA9 

NB_MD55 

NB_MD30 

MD57 

SMAB2 

NB_MD13 

NB_DQS0 

NB_BA1 

NB_MD1 

NB_MD29 

NB_MD2 

NB_MD19 

NB_DQS3 

MD19 

MA0 

NB_MD46 

NB_MD59 

MD18 

MCB0 

MD40 

MD60 

MD61 

MD55 

MD35 

DQS7 

NB_MD26 

NB_MD11 

NB_MD8 

MA11 

MD6 

MA10 

NB_DQS2 

NB_MD48 

NB_MD16 

DQS3 

NB_MD4 

MD0 

MD27 

DM0 

NB_MD42 

CS#0 

MD25 

MD63 

NB_MD33 

NB_MD25 

MD43 

NB_MD9 

MD47 

MD30 

NB_DM3 

NB_MD52 

NB_DM0 

SMAB4 

NB_MD43 

NB_MD34 

NB_MD38 

NB_DQS4 

NB_DM4 

NB_CB7 

MCB3 

MCB7 

MD15 

MD17 

MD10 

MD16 

MD21 

MD20 

MD11 

MD14 

NB_CB4 

NB_CB2 

NB_CB3 

MD46 

MD42 

MD36 

MD37 

DM4 

MD38 

DQS4 

MD33 

MD34 

MD32 

DM1 

MD3 

MD13 

MD8 

MD12 

MD7 

DQS1 

MD9 

MCB4 

DQS8 

SMA[1..2] 

SMA[4..5] 

SMA1 

SMA2 

SMA4 

SMA5 

NB_MA0 

NB_MA3 

NB_MA11 MA11 

MCB0 

CKE1 

CS#0 

MD49 

BA0 

SMA1 

DQS5 

DQS1 

MD43 

MD0 

MD50 

MD34 

MD42 

SMBDATA 

MD26 

MCB2 

SMA5 

MD59 

MD24 

MD11 

MD16 

CLK_DDR0 

CLK_DDR2# 

MCB3 

MD58 

MD27 

MD48 

MD32 

MD3 

CLK_DDR0# 

MD2 

MD51 

MA12 

MD1 

WE# 

MD25 

MA3 

CLK_DDR2 

MD17 

MD40 

MD35 

MD18 

MCB1 

MD8 

MA10 

SMBCLK 

DQS3 

DQS7 

MA9 

MA7 

DQS4 

MD10 

DQS6 

DQS8 

MD41 

MD56 

DQS2 

MD9 

DQS0 

MD19 

MD57 

MD33 

+DDR_VREF 

+3V 

GND 

+1.25V_DDR 

+DDR_VREF 

GND 

+2.5V_DDR 

+2.5V_DDR 

GND 

GND 

+2.5V_DDR 

+1.25V_DDR 

+2.5V_DDR 

GND 

GND 

+DDR_VREF 

GND 

+2.5V_DDR 

+1.25V_DDR 

GND 

+1.25V_DDR 

+3V 

R214 56 0603 

1 2 

C608 

0.1U 

0603D 

1 

2 

C208 

0.01U 

0603 

1 

2 

C221 

0.01U 

0603 

1 

2 

C186 

0.1U 

50V 

0603 

1 

2 

C153 

0.1U 

16V 

0603 

1 

2 

R186 

75 

0603 

0.5% 

1 

2 

C236 

0.01U 

0603 

1 

2 

C257 

0.1U 

50V 

0603 

1 

2 

RP12 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

R194 56 

1 2 

C232 

0.01U 

0603 

1 

2 

C151 

0.1U 

16V 

0603 

1 

2 

C203 

0.01U 

0603 

1 

2 

J514 

0.6MM/200P/H5.2 

QUASAR 

CA0115-200N01 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

46 

48 

50 

52 

54 

56 

58 

60 

62 

64 

66 

68 

70 

72 

74 

76 

78 

80 

82 

84 

86 

88 

90 

92 

94 

96 

98 

100 

102 

104 

106 

108 

110 

112 

114 

116 

118 

120 

122 

124 

126 

128 

130 

132 

134 

136 

138 

140 

142 

144 

146 

148 

150 

152 

154 

156 

158 

160 

162 

164 

166 

168 

170 

172 

174 

176 

178 

180 

182 

184 

186 

188 

190 

192 

194 

196 

198 

200 

41 

43 

45 

47 

49 

51 

53 

55 

57 

59 

61 

63 

65 

67 

69 

71 

73 

75 

77 

79 

81 

83 

85 

87 

89 

91 

93 

95 

97 

99 

101 

103 

105 

107 

109 

111 

113 

115 

117 

119 

121 

123 

125 

127 

129 

131 

133 

135 

137 

139 

141 

143 

145 

147 

149 

151 

153 

155 

157 

159 

161 

163 

165 

167 

169 

171 

173 

175 

177 

179 

181 

183 

185 

187 

189 

191 

193 

195 

197 

199 

C240 

0.01U 

0603 

1 

2 

C175 

0.01U 

0603 

1 

2 

C149 

0.1U 

16V 

0603 

1 

2 

C206 

0.01U 

0603 

1 

2 

C263 

0.1U 

50V 

0603 

1 

2 

C231 

0.01U 

0603 

1 

2 

C247 

0.01U 

0603 

1 

2 

RP13 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

RP26 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

C207 

0.1U 

50V 

0603 

1 

2 

C163 

0.1U 

50V 

0603 

1 

2 

R221 56 

1 2 

C226 

0.01U 

0603 

1 

2 

RP28 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

RP24 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

R219 56 0603 

1 2 

C195 

0.01U 

0603 

1 

2 

RP34 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C150 

0.01U 

0603D 

1 

2 

RP19 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

C218 

0.1U 

0603D 

1 

2 

C223 

0.01U 

0603 

1 

2 

R216 10 0603 

1 2 

C268 

0.01U 

0603 

1 

2 

RP18 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

R215 56 0603 

1 2 

C599 

0.1U 

0603D 

1 

2 

C154 

0.01U 

0603D 

1 

2 

C169 

0.1U 

50V 

0603 

1 

2 

C210 

0.1U 

50V 

0603 

1 

2 

C217 

0.01U 

0603 

1 

2 

C168 

1U 

0603D 

1 

2 

C237 

0.01U 

0603 

1 

2 

RP16 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

RP15 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

RP11 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C216 

0.1U 

50V 

0603 

1 

2 

C160 

0.01U 

0603 

1 

2 

RP31 

10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

RP14 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

C266 

0.01U 

0603 

1 

2 

RP17 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C254 

0.01U 

0603 

1 

2 

RP22 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C215 

0.01U 

0603 

1 

2 

R226 56 0603 

1 2 

C272 

0.1U 

50V 

0603 

1 

2 

C270 

1U 

0603D 

1 

2 

C271 

0.1U 

0603D 

1 

2 

C229 

0.1U 

0603D 

1 

2 

C253 

1U 

0603D 

1 

2 

RP29 

56*4 

1206 

1 

2 

3 

4 

8 

7 

6 

5 

C258 

0.01U 

0603 

1 

2 

RP21 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

RP37 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C274 

10U 

10V 

1206 

1 

2 

RP38 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

R200 56 

1 2 

C225 

0.01U 

0603 

1 

2 

C245 

0.01U 

0603 

1 

2 

C256 

0.01U 

0603 

1 

2 

R185 

75 

0603 

0.5% 

1 

2 

RP25 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C259 

0.01U 

0603 

1 

2 

R231 56 

1 2 

J513 

0.6MM/200P/H9.2 

QUASAR 

CA0145-200N01 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

46 

48 

50 

52 

54 

56 

58 

60 

62 

64 

66 

68 

70 

72 

74 

76 

78 

80 

82 

84 

86 

88 

90 

92 

94 

96 

98 

100 

102 

104 

106 

108 

110 

112 

114 

116 

118 

120 

122 

124 

126 

128 

130 

132 

134 

136 

138 

140 

142 

144 

146 

148 

150 

152 

154 

156 

158 

160 

162 

164 

166 

168 

170 

172 

174 

176 

178 

180 

182 

184 

186 

188 

190 

192 

194 

196 

198 

200 

41 

43 

45 

47 

49 

51 

53 

55 

57 

59 

61 

63 

65 

67 

69 

71 

73 

75 

77 

79 

81 

83 

85 

87 

89 

91 

93 

95 

97 

99 

101 

103 

105 

107 

109 

111 

113 

115 

117 

119 

121 

123 

125 

127 

129 

131 

133 

135 

137 

139 

141 

143 

145 

147 

149 

151 

153 

155 

157 

159 

161 

163 

165 

167 

169 

171 

173 

175 

177 

179 

181 

183 

185 

187 

189 

191 

193 

195 

197 

199 

C243 

0.01U 

0603 

1 

2 

RP36 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

R225 10 0603 

1 2 

RP20 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C185 

0.1U 

0603D 

1 

2 

C605 

0.1U 

0603D 

1 

2 

C228 

0.01U 

0603 

1 

2 

C251 

0.01U 

0603 

1 

2 

C196 

0.01U 

0603 

1 

2 

RP27 

56*4 

1206 

1 

2 

3 

4 

8 

7 

6 

5 

RP35 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

C188 

0.01U 

0603 

1 

2 

C174 

0.1U 

50V 

0603 

1 

2 

C182 

0.01U 

0603 

1 

2 

C145 

10U 

10V 

1206 

1 

2 

C246 

0.1U 

50V 

0603 

1 

2 

RP32 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

C152 

0.1U 

16V 

0603 

1 

2 

RP33 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C179 

0.01U 

0603 

1 

2 

RP23 

56*4 

1206 

1 

2 

3 

4 

8 

7 

6 

5 

RP30 

56*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

C197 

0.01U 

0603 

1 

2 

C265 

0.01U 

0603 

1 

2 

RP40 10*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

C239 

0.01U 

0603 

1 

2 

NB_BA0 

6 

NB_BA1 

6 

NB_RAS# 

6 

NB_WE# 

6 

NB_CAS# 

6 

CKE2 

6 

CKE0 

6 

CKE3 

6 

CKE1 

6 

CS#2 

6 

CS#0 

6 

CS#3 

6 

CS#1 

6 

CLK_DDR1 

6 

CLK_DDR0 

6 

CLK_DDR1# 

6 

CLK_DDR0# 

6 

CLK_DDR3 

6 

CLK_DDR2 

6 

CLK_DDR3# 

6 

CLK_DDR2# 

6 

CLK_DDR5 

6 

CLK_DDR4 

6 

CLK_DDR5# 

6 

CLK_DDR4# 

6 

NB_MA[6..12] 

6 

NB_MD[0..63] 

6 

NB_DM[0..8] 

6 

NB_DQS[0..7] 

6 

NB_CB[0..7] 

6 

SMAB[4..5] 

6 

SMAB[1..2] 

6 

SMA[1..2] 

6 

SMA[4..5] 

6 

NB_MA0 

6 

NB_MA3 

6 

SMBDATA 

4,10,14 

SMBCLK 

4,10,14 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

Place near 

to 7011. 

Default NTSC 

RDDP recommend 

1K ohm resistor 

411675300001 03 


C 

8 29 


Title 

Size 

Document 

Number 

Rev 


XOUT 

TV_CRMA 

TV_LUMA 

TV_CRMA 

TV_LUMA 

TV_DDCK 

DVOCD0 

DVOCD9 

DVOCD[0..11] 

XOUT 

DVOCD7 

XIN 

TV_COMP 

DVOCD4 

DVOCD2 

TV_DDDA 

DVOCD1 

DVOVREF 

DVOCD8 

DVOCD6 

DVOCD10 

DVOCD5 

TV_COMP DVOCD11 

DVOCD3 

XIN 

TV_DDCK 

TV_DDDA 

GND 

+1.5V 

GND GND 

TV_GND GND 

GND 

+3V 

TV_GND 

TV_GND 

TV_GND 

+3V +3V 

+3V 

GND 

GND GND 

GND 

GND 

GND 

+1.5V 

GND 

GND 

+3V 

GND 

+3V 

+1.5V 

+1.5V 

+3V 

+3V 

+3V 

GND 

+3V 

+3V 

C536 

100P 

0603 

10% 

1 

2 

R574 

330 

0603 

1 

2 

C118 

270P 

0603 

10% 

1 

2 

C164 

0.1U 

50V 

0603 

1 

2 

R184 

330/NA 

0603 

1 

2 

R580 

330 

0603 

1 

2 

R206 

10K 

0603 

1 

2 

D5 

BAV99/NA 

1 

2 

3 

C202 

10U 

10V 

1206 

1 

2 

C148 

0.1U 

50V 

0603 

1 

2 

C199 

0.1U 

50V 

0603 

1 

2 

L511 

120Z/100M 

1 2 

C543 

33P 

1 2 

L12 600Z/100M/NA 

1 2 

C572 

20P 

0603 

5% 

1 

2 

RP501 

75*4 

1206 

1 

2 

3 

4 

8 

7 

6 

5 

L11 600Z/100M/NA 

1 2 

X501 

14.318MHZ 

1 3 

2 

4 

C530 

100P 

0603 

10% 

1 

2 

R189 

10K 

0603 

1 

2 

R147 

0/NA 

0805C_DFS 

1 2 

C114 

270P 

0603 

10% 

1 

2 

R575 0/NA 

1 2 

R578 

8.2K/NA 

0603 

1 

2 

J508 

7P/RA 

SUYIN 

33007S-07T1-C 

331870007007 

1 

2 

3 

4 

5 

6 

GND1 

GND2 

7 

1 

2 

3 

4 

5 

6 

GND1 

GND2 

7 

L510 

120Z/100M 

1 2 

C144 

10U 

10V 

1206 

1 

2 

C198 

0.1U 

50V 

0603 

1 

2 

C147 

0.1U 

50V 

0603 

1 

2 

C548 

33P 

1 2 

C165 

0.1U 

50V 

0603 

1 

2 

R210 

1K 

0603 

1 

2 

R193 

10K 

0603 

1 

2 

D6 

BAV99/NA 

1 

2 

3 

R199 

10K 

0603 

1 

2 

R202 

0 

0805C 

1 

2 

C562 

100P 

0603 

10% 

1 

2 

C581 

20P 

0603 

5% 

1 

2 

R579 

1M/NA 

1 2 

C126 

270P 

0603 

10% 

1 

2 

C570 

0.1U 

50V 

0603 

1 

2 

L17 

120Z/100M 

1608 

1 2 

R211 

1K 

0603 

1 

2 

U7 

CH7011A 

PQFP64_0.5MM 

2 

9 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

63 

62 

61 

60 

59 

58 

55 

54 

53 

52 

51 

50 

7 

8 

3 

4 

5 

10 

13 

14 

15 

35 

36 

37 

38 

39 

42 

43 

46 

47 

48 

56 

57 

6 

11 

64 

16 

17 

34 

40 

41 

18 

33 

44 

1 

12 

45 

49 

NC0 

NC1 

NC2 

NC3 

NC4 

NC5 

NC6 

NC7 

NC8 

NC9 

NC10 

NC11 

NC12 

NC13 

NC14 

NC15 

D[0] 

D[1] 

D[2] 

D[3] 

D[4] 

D[5] 

D[6] 

D[7] 

D[8] 

D[9] 

D[10] 

D[11] 

GPIO[1] 

GPIO[0] 

VREF 

H 

V 

AS 

RESET* 

SPD 

SPC 

ISET 

CVBS 

Y/G 

C/R 

CVBS/B 

XI/FIN 

XO 

P-OUT 

BCO 

C/HSYNC 

XCLK* 

XCLK 

DGND_0 

DGND_1 

DGND_2 

AGND_0 

AGND_1 

GND_0 

GND_1 

AGND_2 

AVDD_0 

VDD 

AVDD_1 

DVDD_0 

DVDD_1 

DVDDV 

DVDD_2 

C201 

10U 

10V 

1206 

1 

2 

D 

S 

Q15 

2N7002 

G 

D 

S 

C576 

0.1U 

50V 

0603 

1 

2 

D 

S 

Q16 

2N7002 

G 

D 

S 

C184 

0.1U 

50V 

0603 

1 

2 

R581 

8.2K/NA 

0603 

1 

2 

C529 

33P 

1 2 

R584 140 

1 2 

D7 

BAV99/NA 

1 

2 

3 

L518 

120Z/100M 

1 2 

R192 0/NA 

1 2 

R188 

8.2K 

0603 

1 

2 

DVOCD[0..11] 5 

DVOCVSYNC 

5 

DVOCCLK# 

5 

DVOCCLK 

5 

TV_PCIRST# 

9 

POUT/DET# 

5 

DVOVREF 

5 

DVOCFLDSTL 

5 

DVOCHSYNC 

5 

MI2CDATA 

5 

MI2CCLK 

5 

DVOBCINTR# 5 

VIDEO_L 12 

VIDEO_R 12 


GND 

5 

5 

Dedicate for USB2.0 

can't use as ICH_ 

GPIO5 

1 

+VCC_RTC 

GND 

RTC_RST# 

GND 

RTC_VBIAS 

VDD5 

4 

GND GND 

GND GND 

4 

+3V 

3 

2 

1 

U516 

VOUT 

VIN 

GND0 

NC1 

NC0 

4 

5 

AME8800AEEV 

SOT25 

1 

2 

+3V 

R122 0/NA 0603D_DFS 

R136 0/NA 0603D_DFS 

R161 0/NA 0603D_DFS 

INT_PIRQA# 1 2 D5 

PIRQA# 

18 INT_PIRQB# 

1 2 C2 

INT_PIRQC# 

PIRQB# 

1 2 B4 

PIRQC# 

17 INT_PIRQD# 

A3 

PIRQD# 

16 INT_PIRQE# 

C8 

PIRQE#/GPI0 2 

17,18 INT_PIRQF# 

D7 

PIRQF#/GPIO 3 

15 INT_PIRQG# 

C3 

ICH_GPIO5 

PIRQG#/GPIO 4 

C4 

PIRQH#/GPIO 5 

D 

PCI_REQ4# B6 

REQ# 4 

17 PCI_REQ3# 

C7 

REQ# 3 

18 PCI_REQ2# 

B3 

REQ# 2 

16 PCI_REQ1# 

A2 

REQ# 1 

15 PCI_REQ0# 

B1 

REQ# 0 

ICH_GPIO1 A6 

CRT_IN# 

REQB#/REQ5#/GPIO 1 

14 CRT_IN# 

B5 

REQA#/GPIO 0 

PCI_GNT4# D6 

GNT# 4 

17 PCI_GNT3# 

B7 

GNT# 3 

18 PCI_GNT2# 

A7 

GNT# 2 

16 PCI_GNT1# 

E6 

GNT# 1 

15 PCI_GNT0# 

C1 

GNT# 0 

11 PIDE_OFF# 

C5 

GNTB#/GNT5#/GPIO 17 

11 SIDE_OFF# 

E8 

GNTA#/GPIO 16 

15,16,17,18 PCI_FRAME# 

F1 

FRAME# 

15,16,17,18 PCI_IRDY# 

L5 

IRDY# 

15,16,17,18 PCI_TRDY# 

F2 

TRDY# 

15,16,17,18 PCI_DEVSEL# 

M3 

DEVSEL# 

15,16,17,18 PCI_STOP# 

F3 

STOP# 

15,16,17,18 PCI_PAR 

G1 

PAR 

15,16,17,18 PCI_PERR# 

L4 

PCI_LOCK# 

PERR# 

M2 

PLOCK# 

17,18 PCI_SERR# 

K5 

SERR# 

10,15,16,17,18,20 PCI_PME# 

W2 

PCIRST# 

PME# 

U5 

PCIRST# 

4 PCICLK_ICH 

P5 

PCICLK 

ICH4 

BGA360_25_36 

C 

+3V 

INT_PIRQB# 

1 

8 RP4 

PCI_GNT4# 

2 

7 8.2K*4 

PCI_REQ2# 

3 

6 1206 

INT_PIRQC# 

4 

5 

INT_PIRQE# R150 0603 1 2 8.2K 

INT_PIRQF# R539 0603 1 2 8.2K 

INT_PIRQA# R123 0603 1 2 8.2K 

ICH_GPIO5 R171 0603 1 2 8.2K 

SIDE_OFF# 

1 

8 RP7 

PCI_REQ4# 

2 

7 8.2K*4 

PIDE_OFF# 

3 

6 1206 

PCI_REQ3# 

4 

5 

PCI_REQ0# 

R132 1 2 8.2K 

0603 

PCI_FRAME# 

1 

8 RP2 

PCI_IRDY# 

2 

7 8.2K*4 

PCI_TRDY# 

3 

6 1206 

PCI_STOP# 

4 

5 

ICH_GPIO1 

R151 1 2 100K 

0603 

ICH_GPIO21 

1 

8 RP1 

PCI_SERR# 

2 

7 8.2K*4 

PCI_PERR# 

3 

6 1206 

PCI_DEVSEL# 

4 

5 

INT_PIRQD# R152 1 2 8.2K 

0603 

PCI_REQ1# R153 1 2 8.2K 

0603 

B 

PCI_LOCK# R92 1 2 8.2K 

0603 

CRT_IN# 

R660 1 2 8.2K 

0603 

INT_PIRQG# R78 1 2 8.2K 

0603 

VDD3_RTC 

U3B 

AD[0..31] 

AD31 

AD[0..31] 15,16,17,18 

P4 

AD31 

D2 AD30 

AD30 

R1 AD29 

AD29 

D3 AD28 

AD28 

P2 AD27 

AD27 

E1 AD26 

AD26 

P1 AD25 

AD25 

E2 AD24 

AD24 

M5 AD23 

AD23 

E4 AD22 

AD22 

N3 AD21 

AD21 

E3 AD20 

AD20 

N2 AD19 

AD19 

E5 AD18 

AD18 

N1 AD17 

AD17 

F4 AD16 

AD16 

F5 AD15 

AD15 

L3 AD14 

AD14 

H2 AD13 

AD13 

L2 AD12 

AD12 

G4 AD11 

PCIRST# 

AD11 

L1 AD10 

AD10 

G2 AD9 

AD9 

K2 AD8 

AD8 

J5 AD7 

AD7 

H4 AD6 

AD6 

J4 AD5 

AD5 

G5 AD4 

AD4 

K1 AD3 

AD3 

H3 AD2 

AD2 

J3 AD1 

AD1 

H5 AD0 

AD0 

CBE#[0..3] 

CBE#3 

CBE#[0..3] 15,16,17,18 

N4 

C/BE#3 

M4 CBE#2 

C/BE#2 

K4 CBE#1 

C/BE#1 

J2 CBE#0 

C/BE#0 

0/NA 

0603D_DFS 

U3D 

R532 1 2 

J19 

APICCLK 

H19 

R538 

APICD_0 

1 2 

K20 

10K 

APICD_1 

HSTPCLK# 

3 HSTPCLK# 

V23 

GND 

STPCLK# 

3 HA20M# 

AB23 

A20M# 

3 HSLP# 

U21 

R73 

CPUSLP# 

3 HPWRGD 

1 2 Y23 

0/NA 

CPUPWRGD 

3 HINTR 

AB22 

0603D_DFS 

INTR 

3 HNMI 

V21 

NMI 

3 HSMI# 

W23 

SMI# 

3 HIGNNE# 

W21 

A20_GATE 

IGNNE# 

Y22 

A20GATE 

20 HRCIN# 

U22 

RCIN# 

10 CPU_FERR# 

AA21 

FERR# 

3 HINIT# 

V22 

INIT# 

10,18,19 SERIRQ 

J22 

SERIRQ 

19 LFRAME# 

T5 

LFRAME#/FWH4 

19 LDRQ0# 

U3 

LDRQ1# 

LDRQ0# 

U4 

LDRQ1# 

LAD0 T2 

LAD1 

LAD0/FWH0 

R4 

LAD[0..3] LAD2 

LAD1/FWH1 

19 LAD[0..3] 

T4 

LAD3 

LAD2/FWH2 

U2 

LAD3/FWH3 

SUSCLK 

5 SUSCLK 

AA4 

INTRUDER# SUSCLK 

W6 

RTC_RST# 

INTRUDER# 

W7 

RTCRST# 

5,20 PWROK 

AB6 

PWROK 

20 RSMRST# 

AA6 

RSMRST# 

+VCC_RTC 

AB5 

RTC_VBIAS 

VCCRTC 

Y6 

RTC_X1 

VBIAS 

AC7 

RTC_X2 

RTCX1 

AC6 

RTCX2 

10,29 DPRSLPVR 

1 2 V20 

R72 0/NA 

DPRSLPVR 

3,5 HDPSLP# 

U23 

0603D_DFS 

DPSLP# 

ICH4 

BGA360_25_36 

JL5 

+3V 

U3A 

1 2 

LPC_PCIRST# 19 

JP_NET10 

A5 

VCC3_3 

U2A 

B2 

VCC3_3 

1 

JL6 

H6 

VCC3_3 

3 

1 2 

PCIRST#0 11,22 

J1 

2 

JP_NET10 

VCC3_3 

K6 

VCC3_3 

M10 

VCC3_3 

74AHC08_V 

JL7 

P6 

VCC3_3 

TSSOP14 

1 2 

CB_PCIRST# 18 

U1 

JP_NET10 

VCC3_3 

P12 

VCC3_3 

V10 

VCC3_3 

V16 

VCC3_3 

GND 

V18 

VCC3_3 

AC8 

VCC3_3 

AC17 

+3V 

VCC3_3 

H18 

VCC3_3 

J18 

JL8 

+LAN_3V 

VCC3_3 

1 2 

MCH_PCIRST# 5 

JP_NET10 

VDD3 

E9 

VCCLAN3_3/VCCSUS3_3 

U2B 

F9 


4 

JL9 

E11 

VCCSUS3_3 

6 

1 2 

PCIRST#1 14,21 

F10 

JP_NET10 

VCCSUS3_3 

5 

V9 

VCCSUS3_3 

V8 

VCCSUS3_3 

74AHC08_V 

JL10 

V7 

VCCSUS3_3 

TSSOP14 

1 2 

LAN_PCIRST# 16 

F15 

JP_NET10 

VCCSUS3_3 

F16 

VCCSUS3_3 

F17 

VCCSUS3_3 

F18 

VCCSUS3_3 

GND 

K14 

+1.5V 

VCCSUS3_3 

+3V 

K10 

VCC1_5 

K12 

VCC1_5 

JL11 

K18 

VCC1_5 

1 2 

1394_PCIRST# 15 

K22 

JP_NET10 

VCC1_5 

P10 

VCC1_5 

U2C 

T18 

+VHI_ICH 

VCC1_5 

9 

JL12 

V14 

VCC1_5 

8 

1 2 

MINIPCI_PCIRST# 17 

U19 

VCC1_5 

10 

JP_NET10 

+1.5V 

1 2 

L23 

VCCHI0 

M14 

VCCHI1 

74AHC08_V 

JL13 

R100 0/NA 

P18 

VCCHI2 

TSSOP14 

1 2 

0805C_DFS 

TV_PCIRST# 8 

T22 

JP_NET10 

+LAN_1.5V 

VCCHI3 

VDD1.5 

F6 


GND 

F7 


E12 

VCCSUS1_5 

R6 

VCCSUS1_5 

C515 C525 C523 C526 C514 

T6 

VCCSUS1_5 

10U 0.1U 0.1U 0.1U 0.1U 

U6 

1206 0603 0603 0603 0603 

VCCSUS1_5 

G18 

R2 

10V 50V 50V 50V 50V 

VCCSUS1_5 

E13 

AGPBUSY#/GPIO 6 

AGPBUSY# 5 

VCCSUS1_5 

R3 

F14 

GPIO 7 

KBD_US/JP# 20 

VCCSUS1_5 

V4 

E20 

GPIO 8 

EXTSMI# 10,20 

VCCSUS1_5 

GND 

V5 

V5REF E7 

GPIO 12 

SCI# 10,20 

V5REF1 

W3 

V6 

GPIO 13 

WAKE_UP# 10,20 

V5REF2 

Y21 

+VCCP 

V5REF_SUS E15 

STP_PCI/GPIO 18 

W18 SUSA# 

STOP_PCI# 4 

TP550 

V5REF_SUS 

1 

SLP_S1#/GPIO 19 

W19 

P14 

STP_CPU#/GPIO 20 

T3 ICH_GPIO21 

STOP_CPU# 4,29 

V_CPU_IO 

U18 

C3_STAT#/GPIO 21 

Y20 

+1.5V 

V_CPU_IO 

AA23 

CPUPERF#/GPIO 22 

CPUPERF# 3 

J21 

1 TP508 

V_CPU_IO 

SSMUXSEL/GPIO 23 

C55 C513 C518 

AC2 

10U 0.1U 0.1U 

C22 

CLKRUN#/GPIO 24 

PCLKRUN# 10,17,18,19 

V2 

1206 0603 0603 

VCCPLL 

1 

GPIO 25 

W1 

1 TP4 

10V 50V 50V 

GPIO 27 

C521 

D1 

W4 

1 TP543 

VSS 

1U 

C23 

GPIO 28 

TP544 

0603 

VSS 

C21 

VSS 

C19 

VSS 

Y4 

C17 

SLP_S3# 

Y2 SLP_S4# 

SUSB# 3,4,18,20,21,22,26,28,29 

VSS 

C15 

SLP_S4# 

AA2 SLP_S5# 

VSS 

SLP_S5# 

GND 

C6 

Y1 

+3V 

VSS 

B22 

RI# 

ICH_RI# 16 

VSS 

AA1 

B20 

PWRBTN# 

ICH_PWRBTN# 20 

VSS 

Y3 

B18 

SYS_RESET# 

ICH_SYS_RESET# 10 

Y5 

LDRQ1# 

VSS 

1 2 

B16 

LANRST# 

ICH_LAN_RST# 10 

VSS 

AB2 

B12 

BATLOW#/TP[ 0 ] 

ICH_BATLOW# 10 

VSS 

AB3 1 2 

R528 10K/NA 

B9 

SUS_STAT#/LPCPD 

SUS_STAT# 19 

V19 R45 0/NA 

ICH_VGATE 

VSS 

A22 

VGATE/VRMPWRGD 

VSS 

W20 0603D_DFS 

A20 

THERMTRIP# 

CPU_THRMTRIP# 10 

V1 1 2 

+VCC_RTC 

VSS 

A18 

THRM# 

SB_THRM# 20 

R85 0/NA 

VSS 

A16 

AC3 0603D_DFS 

VSS 

A4 

SMILINK 0 

SMLINK0 10 

AB1 

INTRUDER# 

VSS 

1 2 

A1 

SMLINK 1 

SMLINK1 10 

VSS 

AB4 

SMBDATA 

SMB_DATA 10 

AC4 

R29 10K 

SMBCLK 

SMB_CLK 10 

ICH4 

AA5 

SMBALERT#/GPIO 11 

SMBALERT# 10 

BGA360_25_36 

H23 

SPKR 

SBSPKR 10,12 

GND 

J23 

CLK14 

14M_ICH 4 

HSTPCLK# 1 2 R84 

0603 

0/NA 

0603D_DFS 

+5V +3V 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VSS 

VDD5 

D22 

AC23 

AC18 

AC14 

AC10 

AC5 

AC1 

AB20 

AB7 

AA22 

AA16 

AA12 

AA9 

AA3 

Y19 

Y7 

W22 

W8 

W5 

V17 

V15 

V3 

U20 

T23 

T19 

T1 

R21 

R18 

R5 

P22 

P20 

P13 

P11 

P3 

N23 

N21 

N19 

N14 

N13 

N12 

N11 

N10 

N5 

M13 

M12 

M11 

M1 

M22 

L21 

L14 

L13 

L12 

L11 

L10 

K23 

M20 

K19 

K13 

K11 

K3 

J6 

H1 

G21 

G19 

G6 

G3 

F8 

E22 

E21 

E19 

E18 

E17 

E16 

E14 

E10 

D23 

D21 

D19 

D17 

D15 

D12 

D8 

D4 

VDD3 

GND 

D 

C 

B 

J511 

1.25MM/ST/MA-2 

ACES 

85205-0200 

2 

1 

1 

2 

R525 

1K 

0603 

1 

2 

1 

2 

D503 

BAV70LT1 

C678 

0.047U 

0603 

3 

C692 

4.7U 

0805 

+80-20% 

VDD3_RTC 

3 

SLP_S4# 

SLP_S5# 

3 

VDD3 

+3V +LAN_3V 

A 

C40 

1 2 

R52 

10M 

0603 

RTC_X1 

29 VRMPWRGD 

PWROK 

12 

13 

U2D 

11 

74AHC08_V 

TSSOP14 

R355 

1 

22 

0603 

2 ICH_VGATE 

+3V 

R680 

10K 

0603 

+1.5V 

GND 

+LAN_1.5V 

+VHI_ICH 

GND 

A 

18P 

C36 

1 2 

X1 

32.768KHZ 

R59 

10M 

0603 

RTC_X2 

GND 

1 

R34 

2 

0/NA 

20 A20GATE 

1 

R681 

2 

0/NA 

A20_GATE 

1 

0805 

2 R545 

0/NA 

0805C_DFS C549 

10U 

1206 

10V 

C546 

0.1U 

0603 

50V 

C96 

1U 

0603 

GND 

C520 

0.1U 

0603 

50V 

C519 

0.1U 

0603 

50V 

Title 


GND 18P 

GND 

Size 

C 

Document 

Number 

411675300001 

Rev 

03 

1 

4 

R515 

1 2 

180K 

0603 

2 

1 

2 

1 

2 

1 

2 

C38 

1U 

0603 


C677 

0.1U 

0603 

50V 

1 

2 

C691 

2.2U 

0805 

+80-20% 

14 

7 

14 

7 

14 

7 

14 

7 

1 

2 

C693 

1U 

0603 

D3 

2 

1 

1 

2 

BAW56 

3 

1 

2 

R63 

4.7K 

0603 

SUSC# 20,27 

+3V 

1 

2 

1 

2 

1 

2 

1 

2 

C134 

10U 

1206 

10V 

1 

2 

1 

2 

1 

2 

1 

2 

1 2 R534 

0805 

0/NA 

0805C_DFS 

C39 

0.1U 

0603 

50V 

2 

1 

2 

1 

2 

1 

2 

2 

1 

2 

1 

2 

C527 

10U 

1206 

10V 

C508 

0.1U 

0603 

50V 

1 

2 

GND 

1 

2 

1 

2 

1 

2 

1 

2 

C533 

0.1U 

0603 

50V 

C87 

0.1U 

0603 

50V 

1 

2 

1 

2 

C102 

0.1U 

0603 

50V 

1 

2 

1 

2 

1 

2 

R537 

1K 

0603 

C534 

1U 

0603 

1 

3 

1 

2 

D502 

GND 

BAT54 

C528 

0.1U 

0603 

50V 

V5REF 

VDD3 

1 

2 

C522 

1U 

0603 

50V 

1 

2 

C511 

1U 

0603 

50V 

1 

2 

1 

2 

1 

2 

1 

R536 

1K 

0603 

C531 

1U 

0603 

C510 

0.1U 

0603 

50V 

C524 

0.1U 

0603 

50V 

GND 

V5REF_SUS 

C538 

0.1U 

0603 

50V 


1 

Sheet 9 of 29 

1 

3 

1 

2 

1 

2 

D501 

BAT54 

C537 

0.1U 

0603 

50V 

1 

2 

C539 

0.1U 

0603 

50V 

1 

2

5 

5 

4 

4 

3 

+VCCP 

D 

17 USBP0+ 

17 USBP0- 

17 USBP1+ 

17 USBP1- 

22 USBP2+ 

22 USBP2- 

22 USBP3+ 

22 USBP3- 

USBOC0# 

17 USBOC0# 

USBOC1# 

22 USBOC1# 

USBOC3# 

22 USBOC3# 

USBOC4# 

USBOC5# 

+3V 

1 2 

R365 47K 

17 WIRELESS_PD# 

14 LCD_ID0 

14 LCD_ID1 

14 LCD_ID2 

22 SIDE_IN# 

11 ICH_SIDE_IN# 

1 2 

R366470 

11 IDERST# 

17 MINIPCI_ACT# 

14 DEBUG_EN# 

11 SIDEDET 

13 SPK_OFF 

11 SIDERST# 

4 USBCLK_ICH 

C20 

D20 

A21 

B21 

C18 

D18 

A19 

B19 

C16 

D16 

A17 

B17 

B15 

C14 

A15 

B14 

A14 

D14 

J20 

G22 

F20 

G20 

F21 

H20 

F23 

H22 

G23 

H21 

F22 

E23 

F19 

U3E 

USBP_0 

USBP_0# 

USBP_1 

USBP_1# 

USBP_2 

USBP_2# 

USBP_3 

USBP_3# 

USBP_4 

USBP_4# 

USBP_5 

USBP_5# 

OC#0 

OC#1 

OC#2 

OC#3 

OC#4 

OC#5 

GPIO 32 

GPIO 33 

GPIO 34 

GPIO 35 

GPIO 36 

GPIO 37 

GPIO 38 

GPIO 39 

GPIO 40 

GPIO 41 

GPIO 42 

GPIO 43 

CLK48 

HI 0 

HI 1 

HI 2 

HI 3 

HI 4 

HI 5 

HI 6 

HI 7 

HI 8 

HI 9 

HI 10 

HI 11 

HI_STB#/HI_STBF 

HI_STB/HI_STBS 

HI_COMP 

HIVSWING 

HIREF 

CLK66 

LANRXD0 

LANRXD1 

LANRXD2 

LANTXD0 

LANTXD1 

LANTXD2 

LANRSTSYNC 

LANCLK 

EE_DIN 

EE_CS 

EE_SHCLK 

EE_DOUT 

L19 

L20 

M19 

M21 

P19 

R19 

T20 

R20 

P23 

L22 

N22 

K21 

N20 

P21 

R23 

R22 

M23 

T21 

A10 

A9 

A11 

B10 

C10 

A12 

B11 

C11 

D11 

D10 

C12 

A8 

HUB_HI[0..10] 

HUB_HI0 

HUB_HI1 

HUB_HI2 

HUB_HI3 

HUB_HI4 

HUB_HI5 

HUB_HI6 

HUB_HI7 

HUB_HI8 

HUB_HI9 

HUB_HI10 

R97 1 2 

GND 

56 

HUB_STB# 5 

HUB_STB 5 

HI_COMP 

HI_VSWING 

HI_VREF 

66M_ICH 4 

1 TP6 

R162 1 2 

10K 

GND 

EE_DOUT 

HUB_HI[0..10] 5 

3 HFERR# 

3 CPU_THRMTRIP_OUT# 

R61 

56 

0603 

R62 

1 

56 

+VCCP 0603 

R69 

56 

0603 

R66 

1 

56 

0603 

2 

2 

SIDE_IN# 

1 

R361 

9,18,19 SERIRQ 

1 

R103 

9,17,18,19 PCLKRUN# 

1 

R46 

1 

0603 

CPU_FERR# 9 

ICH_LAN_RST# 

9 ICH_LAN_RST# 

1 

0603 

CPU_THRMTRIP# 9 

VDD3 +3V 

R31 R44 

2.2K 2.2K 

0603 0603 Q515 

2N7002 

9 SMB_DATA 

D S 

2 0603 

47K 

2 0603 

8.2K 

2 0603 

8.2K 

2 R40 

10K/NA 

2 R55 

10K 

GND 

R662 R663 

10K 10K 

0603 0603 

9,20 EXTSMI# 

9,20 SCI# 

9,20 WAKE_UP# 

9,15,16,17,18,20 PCI_PME# 

VDD3 

1 2 R47 

0603 

47K 

1 2 R32 

0603 

47K 

1 2 R30 

0603 

10K 

1 2 R33 

0603 

10K 

1 2 R68 

0603 

10K 

1 2 R76 

0603 

10K 

SMBDATA 4,7,14 

1 

0603 

1 

0603 

1 

0603 

1 

0603 

SMLINK1 

SMLINK0 

SMBALERT# 

ICH_BATLOW# 

ICH_SYS_RESET# 

SPK_OFF 

2 R524 

10K 

2 R523 

10K 

2 R64 

10K 

2 R79 

10K 

SMLINK1 9 

SMLINK0 9 

SMBALERT# 9 

ICH_BATLOW# 9 

ICH_SYS_RESET# 9 

D 

22.6 ohm , 1% 

RDDP 

recommanded. 

C C 

GND 

GND 

HI_COMP 

R89 

1 2 

48.7 

1 

2 

+1.5V 

R128 

22 

0603 

1% 

B23 

USBRBIAS# 

A23 

USBRBIAS 

HI_VREF 

ICH4 

BGA360_25_36 

1 

2 

C92 

0.01U 

0603 

1 

2 

C93 

0.1U 

0603 

50V 

ACSYNC 

ACSDOUT 

ACBITCLK 

ACRST# 

ACSDIN0 

ACSDIN1 

ACSDIN2 

+1.5V 

1 2 

1 

2 

R90 

487 

1% 

R91 

150 

0603 

GND 

C9 

D9 

B8 

C13 

D13 

A13 

B13 

1 

2 

R149 

10 

0603 

HI_VSWING 

ACSYNC 12,22 

ACSDOUT 12,22 

ACBITCLK 12,22 

ACRST# 12,22 

ACSDIN0 12 

ACSDIN1 22 

1 

2 

C81 

0.01U 

0603 

1 

2 

C82 

0.1U 

0603 

50V 

+1.5V 

1 

2 

1 

2 

R83 

130 

0603 

1% 

R82 

150 

0603 

GND 

VDD3 

1 

2 

1 

R168 

10K 

0603 

2 

R148 

10K 

0603 

1 

2 

1 

2 

USBOC4# 

USBOC5# 

GPIO[18] O MAIN POWER WELL STOP_PCI# 

+VHI_ICH 

B 

1 

4.7K/NA 

2 R70 

0603 

GPIO[19] 

GPIO[20] 

O 

O 

MAIN POWER WELL 


SUSA# 

STOP_CPU# 

B 

11 PD_D[0..15] 

PD_D[0..15] 

PD_D15 

PD_D14 

PD_D13 

PD_D12 

PD_D11 

PD_D10 

PD_D9 

PD_D8 

PD_D7 

PD_D6 

PD_D5 

PD_D4 

PD_D3 

PD_D2 

PD_D1 

PD_D0 

Y11 

W11 

W10 

AB10 

W9 

AC9 

Y9 

AB9 

AA8 

Y8 

AB8 

AA7 

AA10 

Y10 

AC11 

AB11 

U3C 

PDD 15 

PDD 14 

PDD 13 

PDD 12 

PDD 11 

PDD 10 

PDD 9 

PDD 8 

PDD 7 

PDD 6 

PDD 5 

PDD 4 

PDD 3 

PDD 2 

PDD 1 

PDD 0 

SDD 15 

SDD 14 

SDD 13 

SDD 12 

SDD 11 

SDD 10 

SDD 9 

SDD 8 

SDD 7 

SDD 6 

SDD 5 

SDD 4 

SDD 3 

SDD 2 

SDD 1 

SDD 0 

Y17 

AA17 

Y16 

AB16 

Y15 

AA15 

AC15 

Y14 

AA14 

W14 

AB15 

W15 

AC16 

W16 

AB17 

W17 

SD_D15 

SD_D14 

SD_D13 

SD_D12 

SD_D11 

SD_D10 

SD_D9 

SD_D8 

SD_D7 

SD_D6 

SD_D5 

SD_D4 

SD_D3 

SD_D2 

SD_D1 

SD_D0 

SD_D[0..15] 

SD_D[0..15] 11 

9,29 DPRSLPVR 

9,12 SBSPKR 

1 

4.7K 

1 

4.7K/NA 

2 R71 

0603 

GND 

+3V 

2 R106 

0603 

GPIO[21] 

GPIO[22] 

GPIO[23] 

GPIO[24] 

GPIO[25] 

GPIO[27] 

GPIO[28] 

GPIO[32] 

GPIO[33] 

O 

OD 

O 

I/O 

I/O 

I/O 

I/O 

I/O 

I/O 




RESUME POWER WELL 






X 

CPUPERF# 

X 

PCLKRUN# 

X 

X 

X 

WIRELESS_PD# 

LCDID0 

11 PDIOW# 

11 PDDACK# 

11 PDDREQ 

11 PDIOR# 

11 PIORDY 

W12 

Y12 

AA11 

AC12 

AB12 

PDIOW# 

PDDACK# 

PDDREQ 

PDIOR# 

PIORDY 

SDIOW# 

SDDACK# 

SDDREQ 

SDIOR# 

SIORDY 

AA18 

AB19 

AB18 

Y18 

AC19 

SDIOW# 11 

SDDACK# 11 

SDDREQ 11 

SDIOR# 11 

SIORDY 11 

STRAPPING AT RISING EDGE OF PWROK 

GPIO[34] 

GPIO[35] 

GPIO[36] 

I/O 

I/O 

I/O 




LCDID1 

LCDID2 

LCDID3 

STRAPPING PINS FUNCTIONS 

GPIO[37] I/O MAIN POWER WELL ICH_SIDE_IN# 

11 PDA0 

11 PDA1 

11 PDA2 

AA13 

AB13 

W13 

PDA0 

PDA1 

PDA2 

SDA2 

SDA1 

SDA0 

AC21 

AC20 

AA20 

SDA2 11 

SDA1 11 

SDA0 11 

ACSDOUT 

EEDOUT 

SAFE MODE 

RESERVED 

GPIO[38] 

GPIO[39] 

I/O 

I/O 



IDERST# 

MINIPCI_ACT# 

11 PDCS1# 

11 PDCS3# 

Y13 

AB14 

PDCS1# 

PDCS3# 

SDCS1# 

SDCS3# 

AB21 

AC22 

SDCS1# 11 

SDCS3# 11 

GNTA# 

OP-BLOCK SWAP OVERRIDE 

GPIO[40] I/O MAIN POWER WELL DEBUG_EN 

DPRSLPVR 

HUB INTERFACE TERMINATION SCHEME GPIO[41] I/O MAIN POWER WELL SIDEDET 

A 

IRQ14 

IRQ15 

AC13 

AA19 

IRQ14 11 

IRQ15 11 

HUB_ICH_COMP HUB INTERFACE SCHEME(1.0 OR 1.5) GPIO[42] I/O MAIN POWER WELL SPK_OFF 

A 

ICH4 

BGA360_25_36 

SBSPKR 

NO REBOOT 

GPIO[43] I/O MAIN POWER WELL SIDERST# 


3 

9 SMB_CLK 

STRAPPING 

ACSDOUT 

EE_DOUT 

1 2 

4.7K/NA 0603 

1 2 

4.7K/NA 0603 

1 

2 

R170 

R169 

+3V 

GND 

1 

2 

D 

S 

G 

2 

1 2 

R698 0/NA 

GPIO CHARACTERISTIC LIST 

NAME 

GPIO[0] 

GPIO[1] 

GPIO[2] 

GPIO[3] 

GPIO[4] 

GPIO[5] 

GPIO[6] 

GPIO[7] 

GPIO[8] 

GPIO[11] 

GPIO[12] 

GPIO[13] 

GPIO[16] 

GPIO[17] 

2 

D 

S 

G 

1 

2 

Q516 

2N7002 

D S 

1 2 

R699 0/NA 

TYPE 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

I 

O 

O 

1 

2 

+3V VDD3 

POWER PLANE 









RESUME POWER WELL SCI# 

INT_PIRQG# 

RESUME POWER WELL EXTSMI# 

RESUME POWER WELL SMBALERT# 



SMBCLK 4,7,14 

CURRENT DEFINE 

CRT_IN# 

INT_PIRQE# 

INT_PIRQF# 

AGP_BUSY# 

KB_US/JP# 

RESUME POWER WELL WAKE_UP# 

Title 

Size 

C 

X 

Dedicate for USB2.0 

SIDE_OFF# 

PIDE_OFF# 

Document 

Number 

1 


Rev 

411675300001 03 


1 

Sheet 10 of 29

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

Enhance driving force for GPO. 

For Hard-Disk 

Primary EIDE Connector 

R0A reverse the pin definition 

Secondary EIDE Connector 

W/S=16/12/12/16 mils W=12 mils 

For CD-ROM 

Mount 0 ohm 

resistor 

Mount 0 ohm 

resistor 

411675300001 03 


C 

11 29 


Title 

Size 

Document 

Number 

Rev 


C_SDCS1# 

SD_D13 

C_PD_D14 

SD_D11 

C_SD_D1 

SDIOW# 

PD_D8 

C_PD_D9 

PDIOR# 

C_PD_D12 

SDREQ 

C_SD_D7 

C_PD_D11 

C_SD_D13 

PD_D3 

C_PDA1 

C_SDCS3# 

SIORDY 

PD_D14 

SD_D8 

SD_D14 

C_PD_D7 

C_SD_D15 

C_PDA0 

C_PDA2 

SD_D0 

C_PDA2 

PDIOW# 

C_SD_D3 

C_SDIOW# 

C_PDCS3# 

C_PD_D5 

C_PDIOW# 

C_PDDREQ 

SD_D6 

C_PDDACK# 

PD_D0 

C_SD_D10 

C_SDDACK# 

C_SDA1 

PD_D[0..15] 

SD_D15 

C_SD_D11 

SDACK# 

C_RSTDRV1# 

C_PINTRQ 

PDDACK# 

PD_D13 

C_PD_D6 

C_PDIOR# 

C_SD_D0 

HDD_LED# 

C_PDCS1# 

PD_D4 

SDA1 

C_PD_D3 

SD_D10 

SD_D7 

PD_D1 

C_SD_D9 

SDA2 

PDCS1# 

PD_D7 

SD_D1 

C_PD_D12 

C_PD_D14 

C_PIORDY 

C_SD_D12 

C_SD_D4 

C_PD_D10 

PD_D6 

SD_D[0..15] 

SD_D9 

C_PD_D4 

SDCS3# 

C_PD_D11 

PD_D12 

C_PD_D10 

C_SD_D2 

SD_D12 

C_PD_D2 

C_PD_D8 

PD_D2 

C_PD_D7 

C_PD_D15 

PD_D9 

C_RSTDRV1# 

C_SDIOR# 

C_SIORDY 

C_PD_D1 

C_PDCS3# 

SDCS1# 

C_SD_D14 

C_SD_D8 

PDCS3# 

C_SDA0 

PD_D10 

SD_D3 

C_PD_D0 

SD_D2 

C_PD_D13 

PDDREQ 

SD_D5 

PD_D11 

PDA0 

C_PD_D13 

C_SDA2 

SD_D4 

C_SDDREQ 

C_SINTRQ 

C_PD_D15 

PD_D15 

C_PD_D8 

C_PD_D9 

C_SD_D5 

PDA1 

PD_D5 

SDA0 

C_SD_D6 

C_PDA1 

C_PD_D5 

C_PD_D1 

C_PD_D2 

C_PINTRQ 

C_PIORDY 

C_PDDREQ 

C_PD_D0 

C_PDIOR# 

C_PDCS1# 

C_PD_D4 

C_PDA0 

C_PD_D6 

C_PDDACK# 

C_PDIOW# 

C_PD_D3 

PCIRST#0 

C_SDA0 

C_SD_D4 

C_SDDACK# 

C_SINTRQ 

C_SD_D6 

C_SD_D7 

C_SD_D15 

C_SD_D3 

C_SDCS1# 

C_SD_D11 

C_SD_D2 

CDROM_RIGHT 

CDROM_COMM 

CDROM_LEFT 

C_SD_D5 

C_SDIOR# 

C_SD_D8 

C_SD_D1 

C_SD_D0 

C_SD_D13 

C_SDCS3# 

CD_LED# 

C_SDA1 

C_SIORDY 

C_SDIOW# 

C_SDA2 

C_SD_D14 

C_SD_D12 

C_SD_D10 

C_SD_D9 

C_SDDREQ 

PCIRST#0 

C_RSTDRV2# 

C_RSTDRV2# 

B12_A26 

B12_A26 

B3_A15 

B3_A15 

GND 

GND 

+3V 

+3V 

+5V 

GND 

+5V_HDD 

GND 

+3V +3V 

GND 

GND 

GND 

+5V_HDD 

GND 

GND 

+3V 

+3V 

+3V +3V +5V 

GND 

GND 

+5V_CDROM 

GND 

GND 

GND 

GND 

GND 

+5V_CDROM 

GND 

+5V 

GND GND 

+5V_HDD +5V_CDROM 

GND 

GND 

+3V 

+5V 

GND 

GND 

GND 

R370 

10K 

0603 

1 

2 

L24 

120Z/100M 

2012 

1 

2 

C341 

0.1U 

50V 

0603 

1 

2 

RP10 

0*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

RP8 

0*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

RP46 

0*4 

1206 

1 

2 

3 

4 

8 

7 

6 

5 

R51 

8.2K 

0603 

1 

2 

R376 

470 

0603 

1 

2 

C167 

10U 

10V 

1206 

1 

2 

D28 

BAW56 

2 

1 

3 

R357 

10K 

0603 

1 

2 

J509 

MA/26PX2/.5MM 

HIROSE 

FX5-52P-SH3 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

A17 

A18 

A19 

A20 

A21 

A22 

A23 

A24 

A25 

A26 

B1 

B2 

B3 

B4 

B5 

B6 

B7 

B8 

B9 

B10 

B11 

B12 

B13 

B14 

B15 

B16 

B17 

B18 

B19 

B20 

B21 

B22 

B23 

B24 

B25 

B26 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

A17 

A18 

A19 

A20 

A21 

A22 

A23 

A24 

A25 

A26 

B1 

B2 

B3 

B4 

B5 

B6 

B7 

B8 

B9 

B10 

B11 

B12 

B13 

B14 

B15 

B16 

B17 

B18 

B19 

B20 

B21 

B22 

B23 

B24 

B25 

B26 

C264 

1U 

0603 

1 

2 

C338 

10U 

10V 

1206 

1 

2 

R50 

4.7K 

0603 

1 

2 

R172 

5.6K/NA 

0603 

1 

2 

C124 

0.1U 

50V 

0603 

1 

2 

R118 

470/NA 

1 2 

C339 

0.1U 

50V 

0603 

1 

2 

RP42 

0*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

R252 

22 

0603 1 2 

C183 

1U 

0603 

1 

2 

R367 

0/NA 

0603D_DFS 

1 

2 

D26 

BAW56 

2 

1 

3 

R42 

0/NA 

0603D_DFS 

1 2 

J4 

FM/22PX2/RA 

C17802-144XX 

291000024419 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

GND1 

GND2 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

GND1 

GND2 

R305 

5.6K/NA 

0603 

1 

2 

D29 

BAW56 

2 

1 

3 

C156 

1U 

0603 

1 

2 

R99 0/NA 

0603D_DFS 

1 2 

R375 5.6K 

1 2 

C125 

0.1U 

50V 

0603 

1 

2 

C262 

10U 

10V 

1206 

1 

2 

C115 

10U 

10V 

1206 

1 

2 

R80 

10K 

0603 

1 

2 

U23 

SI4788CY 

SO8 

1 

2 

3 

4 5 

7 

6 

8 

VIN 

SOURCE1 

SOURCE2 

SOURCE3 DRAIN3 

DRAIN2 

DRAIN1 

GND 

R1 

Q7 

DTC144TKA 

2 

1 3 

R1 

Q13 

DTC144TKA 

2 

1 3 

RP44 

0*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

R368 

0/NA 

0603 

1 

2 

R196 

22 

0603 1 2 

L29 

120Z/100M 

2012 

1 

2 

R304 

4.7K 

0603 

1 

2 

R256 

10K/NA 

0603 

1 2 

U24 

SI4788CY 

SO8 

1 

2 

3 

4 5 

7 

6 

8 

VIN 

SOURCE1 

SOURCE2 


DRAIN2 

DRAIN1 

GND 

R358 

0/NA 

0603D_DFS 

1 2 

R362 

10K 

0603 

1 

2 

R195 

10K/NA 

0603 

1 

2 

R323 

470 

1 2 

R43 

10K 

0603 

1 

2 

RP9 

0*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 9 

10 

11 

12 

13 

14 

15 

16 

RP43 

0*8 

RPX8 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

RP3 

0*4 

1206 

1 

2 

3 

4 

8 

7 

6 

5 

R156 

8.2K 

0603 

1 

2 

R356 

10K 

0603 

1 

2 

C255 

1U 

0603 

1 

2 

SDA2 

10 

SDCS3# 

10 

IRQ14 

10 

SDCS1# 

10 

SD_D[0..15] 

10 

SIORDY 

10 

PDDACK# 

10 

PD_D[0..15] 

10 

PIORDY 

10 

SDDACK# 

10 

SDA0 

10 

PDA0 

10 

PDIOR# 

10 

PDIOW# 

10 

SDIOW# 

10 

SDDREQ 

10 

PDCS1# 

10 

SDA1 

10 

IRQ15 

10 

PDA1 

10 

PDA2 

10 

PDCS3# 

10 

HDD_LED# 

21 

PDDREQ 

10 

IDERST# 

10 

PCIRST#0 

9,22 

SIDERST# 

10 

SDIOR# 

10 

CDROM_RIGHT 12 

CDROM_COMM 

12 

CD_LED# 

21 

SIDEDET 10 

CDROM_LEFT 

12 

H8_SIDE_IN# 

20 

ICH_SIDE_IN# 10 

PIDE_OFF# 

9 

SIDE_OFF# 

9 


5 

5 

4 

4 

3 

D 

+3V 

AVDDAD 

JS4 

L31 

+5V 

D 

1 2 1 2 

GND 

120Z/100M 

2012 

AGND 

GND 

GND 

CHIP ALC201 EMP202 

Cap pin31: 0.1U X 

Cap pin33: 1U X 

Cap p33/34 X X 

GND 

1 

2 

AGND 

AGND 

C640 

1 2 

0.1U/NA 50V 0603 

R636 

1K/NA 

0603 

1 

2 

1 

1 

2 

2 

GND 

1 

2 

C618 

0.1U/NA 

0603 

50V 

R635 

1K/NA 

0603 

1 

2 

C619 

0.1U/NA 

0603 

50V 

GND 

AGND 

When using an external clock replace C211 

with 0 ohm resistor.(updated 10/19/2001) 

GND 

1 

2 

C644 

0.1U 

0603 

50V 

1 

2 

C633 

0.1U 

0603 

50V 

+5V 

1 

2 

AGND 

SHORT-SMT4 

C315 

10U 

1206 

10V 

C636 1 2 1U 10V 0603 

C642 1 2 1000P 50V 0603 

20mil 

C643 

0.1U 

0603 

50V 

C617 

1 2 

1 

2 

AGND 

H8_AVREF 

R693 

10K 

B 

0603 

L35 

B 

R328 

600Z/100M 

GND 

0 

0805C 

R340 

R654 

1608 

L537 

J519 

3 

5 

4 

L529 

1 2 

120Z/100M 

GND 2012 

AGND 

L36 

1 2 

L13 

1 2 

120Z/100M 

GND 2012 

AGND 

L32 

1 2 

Current selection 

For EMP202 

FREQ. ID1# ID0# 

14.318MHz OPEN OPEN 

27MHz OPEN 1K 

48MHz 1K OPEN 

24.576MHz 1K 1K 

CHIP ALC201 EMP202 

Cap. pin39: 1000P 560P 

Cap. pin41: 1000P 560P 

Cap. pin20: 1U 0.33U 

Cap. pin18: 1U 0.33U 

Cap. pin19: 1U 0.33U 

1 

4.7K 

C331 

4.7U 

0805 

+80-20% 

2 

0603 

1 

4.7K 

C665 

2.2U 

0805 

+80-20% 

2 

0603 

C666 

100P 

0603 

1 2 

600Z/100M 

1608 

AGND 

JO64 

CAGND 

2 

1 

CONN_SMKLGY2313 

PHONE-JACK-LGY2313_0 

331840005013 

120Z/100M 

2012 

1 

2 

40 

43 

44 

45 

46 

47 

48 

1 

9 

4 

7 

25 

38 

26 

42 

37 

MONO_OUT 

39 

ALT_LINE_OUT_L 

41 

ALT_LINE_OUT_R 

29 

AFLT1 

30 

AFLT2 

27 

REFFLT 

28 

VREFOUT 

STAC9750 

PQFP48_0.5MM 

1 

2 

GND 

GND 

AGND AGND AGND 

GND 

R281 

1 2 MODEM_SPK 

10K 

MODEM_SPK 22 

U509 

0603 

LINE/IN/L 

23 C637 1 2 2.2U 0805 +80-20% 

R284 

1K 

0603 

C310 

0.1U/NA 

0603 

LINE/IN/R 

24 C312 1 2 2.2U 0805 +80-20% 

50V 

10,22 ACRST# 

10,22 ACSDOUT 

10 ACSDIN0 

10,22 ACSYNC 

10,22 ACBITCLK 

ACRST# 

ACSDOUT 

ACSDIN0 

ACSYNC 

ACBITCLK 

1 2 

22 R632 0603 

1 2 1 

L527120Z/100M 22 

2 

R631 

11 

5 

8 

10 

6 

RESET# 

SDATA/OUT 

SDATA/IN 

SYNC 

BIT/CLK 

MIC1 

MIC2 

CD/R 

21 

22 

20 

MIC1 C634 1 

MIC2 C635 1 

C632 1 

2 

2 

2 

1U 10V 0603 MIC 

1U 10V 0603 

0.33U 16V 0603 

R309 1 2 6.8K 5% 

AGND 

CDROM_RIGHT 

CDROM_RIGHT 11 

4 14M_CODEC 

1 R265 2 

0/NA 

0603D_DFS 

1 

0.01U 

0603 

2 C292 

1 R630 2 

0603 1M/NA 

X5 

1 2 

1608 

0603 

PC_BEEP 

2 

3 

12 

XTL/IN 

XTL/OUT 

PC_BEEP 

CD/L 

CD/GND 

VIDEO/L 

VIDEO/R 

18 

19 

16 

17 

C628 1 

C631 1 

C625 1 

C627 1 

2 

2 

2 

2 

0.33U 16V 

0.33U 16V 

1U 

1U 

0603 

0603 

R308 

6.8K 

R302 1 2 6.8K 5% 

R313 1 0/NA 2 

0603D_DFS 

R301 R307 

6.8K 0/NA 

CDROM_LEFT 

CDROM_COMM 

CDROM_LEFT 11 

CDROM_COMM 11 

24.576MHZ/NA 

AUX/L 

14 C623 1 2 1U 10V 0603 

5% 5% 0603D_DFS 

C 

C294 

C295 

0603 50V 0.1U/NA 1 2 C652 

31 

BPCFG 

AUX/R 

15 C624 1 2 1U 10V 0603 

MIC1 

C 

10P/NA 

0603 

0/NA 

0603D_DFS 

0603 10V 1U 1 

0603 10V 1U/NA 1 

0603 50V 1000P/NA 1 

2 C641 

2 C650 

2 C639 

32 

33 

34 

FLT3D 

FLTI 

FLTO 

LINE/OUT/L 

LINE/OUT/R 

PHONE 

35 

36 

13 

AOUT_L 

AOUT_R 

C622 1 2 1U 10V 0603 

AGND AGND AGND 

1 

+ 

2 

- 

D5.8/H2.0 

EM147TK 

C651 

1 2 

0.1U/NA 50V 0603 

13 SPDIFOUT 

NC1 

NC2 

NC3 

ID0# 

ID1# 

EAPD 

S/PDIF_OUT 

A 

9,10 SBSPKR 

18 CARDSPK# 

SBSPKR 

C620 

CARDSPK# 1 2 

1 

2 

3 

U508 

A VCC 

B Y 

GND 

5 

4 

0.1U 

50V GND 

0603 

1 2 

R633 

C621 

1 2 PC_BEEP 

0.1U 

0603 

A 

0.1U 

50V 

0603 R629 

NC7S32 

SOT25 

10K 

0603 

R634 

2K 

50V 

47K 

0603 

0603 


1 

2 

DVDD1 

DVDD2 

DVSS1 

DVSS2 

AVDD1 

AVDD2 

AVSS1 

AVSS2 

1 

2 

AGND 

3 

C655 

0.1U 

0603 

50V 

120Z/100M 

2012 

1 

2 

AGND 

C654 

1U 

0603 

10V 

1 

2 

1 2 

R297 0/NA 

VIDEO_L 8 

1 2 

R283 0/NA 

VIDEO_R 8 

C653 1 2 1000P 50V 0603 

C323 

0.1U 

0603 

50V 

1 

2 

1 

2 

AGND AGND 

1 

2 

MONO_OUT 

C638 

1000P/NA 

0603 

1 2 

MONO_OUT 22 

1 

2 

1 

2 

2 

2 

AOUT_L 

1 

2 

AOUT_R 

1 

2 

AOUT_L 13 

AOUT_R 13 

1 

2 

1 

2 

Title 

Size 

C 

1 2 

1 

2 

1 2 

CAGND 

Document 

Number 

C340 

47P 

0603 

10% 

1 2 

JO63 

L538 

600Z/100M 

1608 

1 2 

AGND 

1 


Rev 

411675300001 03 


1 

Sheet 12 of 29

12 AOUT_R 

5 

5 

C326 

C327 R645 

AOUT_R 1 2 

1 2 1 2 RHP_IN 1 2 

ROUT+ 

4 

4 

3 

R650 15K 0603 

4.7U 

4.7U 10K 

D 

16V 

1206 

16V 

1206 

0603 

D 

12 AOUT_L 

R646 

1 2 RLINE_IN 

C318 

C324 R648 

AOUT_L 1 2 

1 2 1 2 LHP_IN 

R649 

1 2 LLINE_IN 

LOUT+ 

C C 

1 

2 

3 

1 

GND 

4.7U 

16V 

1206 

1 

2 

1 

2 

C325 

1 2 

0.1U 

50V 

0603 

4.7U 

16V 

1206 

C646 

1 2 

0.1U 

50V 

0603 

1 

2 

10K 

0603 

10K 

0603 

10K 

0603 

R651 33K 0603 

R652 15K 0603 

+5V 

1 2 

1 2 

1 2 

R653 33K 0603 

1 

2 

1 

2 

1 

2 

C645 

0.1U 

0603 

50V 

1 

2 

1 

2 

C649 

0.1U 

0603 

50V 

1 

2 

AGND 

120Z/100M 

+ C629 

100U 

16V 

CPWX6.6 

1608 

JS5 

1 2 

RLINE_IN 

RHP_IN 

21 

20 

U511 

RLINE IN 

RHP IN 

R OUT+ 

R OUT- 

22 

15 

ROUT+ 

ROUT- 

ROUT+ 22 

ROUT- 22 

J503 

B 

C656 

1U 

0603 

C648 

1U 

0603 

LLINE_IN 

LHP_IN 

C319 

0.1U 

0603 

50V 

4 

5 

6 

19 

14 

16 

11 

9 

8 

LLINE IN 

LHP IN 

L BYPASS 

R BYPASS 

SE/BTL# 

HP/LINE# 

MUTE IN 

MUTE OUT 

SHUTDOWN 

L OUT+ 

L OUT- 

RVDD 

LVDD 

GND0/HS 

GND1/HS 

GND2/HS 

GND3/HS 

NC0 

NC1 

NC2 

3 

10 

18 

7 

1 

12 

13 

24 

2 

17 

23 

LOUT+ 

LOUT- 

+ C630 

100U 

16V 

CPWX6.6 

+ 

L501 

L502 

C664 

100U 

16V 

CPWX6.6 

1 

1 

2 600Z/100M 

2 600Z/100M 

1608 

1608 

JO502 

1 

2 ACES 

ST/MA-2 

85204-0200 

291000020206 

JO503 

B 

AVDDAD 

R311 

15K 

AGND AGND 

AGND 

AMP_SHUTDOWN 

30 

31 

32 

33 

34 

G6 

G7 

G8 

G9 

G10 

G1 

G2 

G3 

G4 

G5 

25 

26 

27 

28 

29 

R324 

1K 

0603 

R330 

1K 

0603 

C329 

100P 

0603 

10% 

C328 

100P 

0603 R327 

10% 22 

R331 

22 

L535 120Z/100M 

1 2 

GND GND 

AVDDAD 

+5V 

R347 

R343 

0603 

APA2020A_GND TSSOP24_TPA0102 

0603 0603 

4.7K 

0603 

10K 

0603 

AGND 

AGND 

L38 600Z/100M 1608 

J518 

DEVICE_DECT# 2 

Q23 

DTC144WK 

AGND AGND AGND AGND 

L534 

DEVICE_DECT# 

PLP3216S/NA 

AGND 

1 2 

DECT_HP#/OPT 

L533 120Z/100M 

1 2 

1 2 

L531 120Z/100M 

1 2 

L37 600Z/100M 1608 

5 

4 

2 

3 

1 

6 

11 

+5V +3V 

1 

3 

12 SPDIFOUT 

1 

1 

L536 

2 

600Z/100M 

2 

1608 

7 

8 

9 

Drive 

IC 

LED 

U18 

Q26 

A 

10 SPK_OFF 

AMP_DOWN 

1 

2 

3 

A VCC 

B Y 

GND 

5 

4 AMP_SHUTDOWN 

DTC144TKA 

AGND 

R1 2 DECT_HP#/OPT 

A 

NC7S32 

Q31 

SOT25 

DTC144TKA 

AGND AGND 

GND 

DEVICE_DECT# 


1 

2 

1 

2 

3 

L530 

1 2 

SHORT-SMT4 

1 

2 

1 2 

1 2 

+5V 

CAGND 

AMP_DOWN 

1 

1 32 

R314 

4.7K 

0603 

R1 

1 

4 

2 

+3V 

1 

2 

2 

3 

R346 

10K 

0603 

2 

1 3 

1 2 

1 2 

Q513 

DTA144WK 

2 

2 

1 

2 

1 

2 

AGND 

L532 120Z/100M 

1 2 

JO58 

1 2 

Title 

JO61 

Size 

C 

2F1138-TJ1 

FOXCONN 

331840010005 

Document 

Number 

1 


Rev 

411675300001 03 


1 

Sheet 13 of 29

5 

5 

GND 

+3V +3V +5V 

+3V 

4 

4 

GND 

GND 

GND 

3 

D 

LCD CONNECTOR 

Q4 

SI4800DY 

SO8 

10 LCD_ID0 

10 LCD_ID1 

10 LCD_ID2 

1 

2 

3 

4 

SW2 

8 

7 

6 

5 

HDS404E 

D 

5 TXCLKOUT1+ 

5 TXCLKOUT1- 

5 TXOUT3+ 

5 TXOUT3- 

5 TXOUT5+ 

5 TXOUT5- 

5 TXOUT2+ 

5 TXOUT2- 

LCDVCC 1 

3 

5 

TXCLKOUT1+ 7 

TXCLKOUT1- 9 

11 

TXOUT3+ 

13 

TXOUT3- 

15 

17 

TXOUT5+ 

19 

TXOUT5- 

21 

23 

TXOUT2+ 

25 

TXOUT2- 

27 

29 

J505 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

TXCLKOUT0+ 

TXCLKOUT0- 

TXOUT4+ 

TXOUT4- 

TXOUT0+ 

TXOUT0- 

TXOUT1+ 

TXOUT1- 

LCDVCC 

TXCLKOUT0+ 5 

C7 

TXCLKOUT0- 5 

1000P 

0603 

TXOUT4+ 5 

TXOUT4- 5 

TXOUT0+ 5 

TXOUT0- 5 

TXOUT1+ 5 

TXOUT1- 5 

1 

2 

R533 

2.2K 

0603 

VGA_DDDA 

B B 

G 

Q502 

2N7002 

S 

D 

S 

D 

1 R516 2 

0/NA 0603 

G 

S 

G 

S 

D 

S Q504 

2N7002 

D 

Q503 

S 

D 

2N7002 

Q505 

2N7002 

D 

GND1 

GND2 

G 

S 

GND1 

GND2 

FM/1MM/ST 

I-PEX 20265-030E 

D 

S 

D 

1 R531 2 

0/NA 0603 

1 

1 

1 

R552 

75/NA 

1% 

2 

2 

2 

R543 

75/NA 

1% 

R544 

75/NA 

1% 

GND 

4 

3 

2 

1 

5 

6 

7 

8 

GND 

1 2 L505120Z/100M 1608 

1 2 L504120Z/100M 1608 

1 2 L503120Z/100M 1608 

CP501 

22P*4 

1206 

L5 1 2 120Z/100M 2012 

1 

2 

1 2 L506 120Z/100M 1608 

1 2 L507 120Z/100M 1608 

1 2 L509 120Z/100M 1608 

1 2 L508 120Z/100M 1608 

C13 

1000P 

0603 

CP503 

22P*4 

1206 

1 

2 

5 

6 

7 

8 

4 

3 

2 

1 

C12 

0.1U 

0603 

50V 

C 

10 DEBUG_EN# 

2 

Q12 

DTC144WK/NA 

4,7,10 SMBCLK 

D S 

VGA_RED 

VGA_DDDA 

6 

1 

11 

12 

C 

+5V 

GND 

Q3 

2N7002 

VGA_GREEN 

VGA_BLUE 

VGA_HSYNC 

VGA_VSYNC 

VGA_DDC2B 

7 

8 

2 

3 

13 

14 

9 

10 

F2 

4,7,10 SMBDATA 

D S 

9 CRT_IN# 

Q501 

VGA_DDCK 

4 

5 

15 

MICROSMDC110 

17 

5 CRT_R 

5 CRT_G 

5 CRT_B 

5 CRT_DDDA 

5 CRT_HSYNC 

5 CRT_VSYNC 

5 CRT_DDCK 

1 

2 

R508 

2.2K 

0603 

A A 


1 

2 

3 

1 

2 

GND 

4 

3 

2 

1 

5 

6 

7 

8 

C11 

10U 

1206 

10V 

1 

2 

3 

2 

1 

CP502 

22P*4 

1206 

S 

C690 

0.1U 

0805 

20% 

1 2 

A 

K 

1 

2 

4 

G 

D1FS4 

D4 

D 

8 

7 

6 

5 

1 3 

+5V 

1 

2 

3 

1 

2 

F1 

MICROSMDC110 

R141 

10K/NA 

0603 

DVMAIN 

1 

1 

1 

R511 

75 

1% 

2 

2 

2 

+3V 

R510 

75 

1% 

GND 

Place near to the 

CRT connector. 

1 

R1 Q6 

R5 470K 

2 

0603 

DTC144TKA 

DDC2B L8 1 2 2012 

120Z/100M 

C95 

10U/NA 

1206 

10V 

1 2 

R509 

75 

1% 

1 

2 

GND 

C5 

0.1U 

0603 

50V 

1 2 

1 

2 

2 

GND 

1 2 

2 

C9 

10U/NA 

1206 

10V 

1 2 

+3V 

1 

2 

D 

S 

R6 

10K 

0603 

G 

2N7002 

1 2 

D2 

BAW56 

D 

S 

G 

2 FPVCC 

JO504 JO508 JO506 JO505 JO507 JO509 JO510 

3 

1 2 

1 

1 2 

1 2 

1 

2 

GND 

4 

3 

2 

1 

5 

6 

7 

8 

GND 

FPVCC 5 

PCIRST#1 9,21 

1 2 

R527 

1K 

0603 

C517 

100P 

0603 

VGA_RED 

VGA_DDC2B 

VGA_GREEN 

VGA_BLUE 

VGA_HSYNC 

VGA_VSYNC 

VGA_DDCK 

Title 

Size 

C 

RP5 

47K*4 

1206 

Document 

Number 

GND 

1 


SHORT-SMT4 

GND_CRT15 

Rev 

411675300001 03 


1 

Sheet 14 of 29 

+3V 

4 

3 

2 

1 

5 

6 

7 

8 

GND 

J507 

RP6 

2.7K*4 

1206 

16 

15P/2R-FM 

CONN_SYN7322S_15GT 

331720015023 

JL502 

2 1 

SHORT-SMT4 

JL501 

2 1

VT6307L 

IDSEL: AD21 

PCI REQ0# 

PCI GNT0# 

PCI INTG# 

5 

5 

1394_VCC 

1 

1394_AVCC 

GND 

1 

2 

C219 

0.1U 

0603 

50V 

1 

2 

C220 

0.1U 

0603 

50V 

1 

1 

2 

GND 

4 

4 

1394_VCC 

3 

B B 

A A 

3 

0: Disable (Default) 

1: Enable 

CARDBUSENA CardBus Mode 

0: Disable (PCI)(Default) 

1: Enable 

PHYCMC Programmable Contender / Bus Manager Capable 

High specifies that the node is capable of 

being a bus manager. 

2 

2 

Title 

Size 

C 

Document 

Number 

+3V 

1 

+3V 1394_AVCC 

D C234 

0.1U 

C241 

0.1U 

C250 

0.1U 

C249 

0.1U 

C248 

0.1U 

C224 

0.1U 

L19 

D 

0603 

50V 

0603 

50V 

0603 

50V 

0603 

50V 

0603 

50V 

0603 

50V 

GND 

1 2 

120Z/100M 

2012 

C 

GND 

AD[0..31] 

U9 

9,16,17,18 AD[0..31] 

AD0 

28 

AD1 

AD0 

27 

AD2 

AD1 

23 

AD3 

AD2 

22 

AD4 

AD3 

21 

AD5 

AD4 

19 

AD6 

AD5 

18 

AD7 

AD6 

17 

AD8 

AD7 

14 

AD9 

AD8 

13 

AD10 

AD9 

12 

AD11 

AD10 

11 

AD12 

AD11 

10 

AD13 

AD12 

7 

AD14 

AD13 

6 

AD15 

AD14 

5 

AD16 

AD15 

120 

AD17 

AD16 

119 

AD18 

AD17 

118 

AD19 

AD18 

117 

AD20 

AD19 

116 

AD21 

AD20 

112 

AD22 

AD21 

110 

AD23 

AD22 

109 

AD24 

AD23 

106 

AD25 

AD24 

105 

AD26 

AD25 

104 

AD27 

AD26 

101 

AD28 

AD27 

100 

AD29 

AD28 

99 

AD30 

AD29 

98 

AD31 

AD30 

97 

CBE#[0..3] 

AD31 

9,16,17,18 CBE#[0..3] 

CBE#0 15 

CBE#1 

CBE0# 

4 

CBE#2 

CBE1# 

122 

CBE#3 

CBE2# 

107 

CBE3# 

9,16,17,18 PCI_FRAME# 

123 

FRAME# 

9,16,17,18 PCI_DEVSEL# 

127 

DEVSEL# 

9,16,17,18 PCI_TRDY# 

126 

TRDY# 

9,16,17,18 PCI_IRDY# 

124 

IRDY# 

9 PCI_GNT0# 

95 

PGNT# 

9 PCI_REQ0# 

96 

AD21 

PREQ# 

2 1 108 

R217 0/NA 

IDSEL 

9 INT_PIRQG# 

91 

0603D_DFS 

INTA# 

4 PCICLK_1394 

93 

PCICLK 

9 1394_PCIRST# 

92 

PCIRST# 

9,16,17,18 PCI_PAR 

3 

PAR 

9,16,17,18 PCI_PERR# 

2 

PERR# 

9,16,17,18 PCI_STOP# 

128 

STOP# 

58 

PHYRST# 

R589 C589 

0/NA 0.1U 

0603 

50V 

1394_PCIRST# 

GND 

54 

PHYPC0 

55 

PHYPC1 

53 

PHYPC2 

52 

PHYCMC 

46 1 2 

12CEEENA 

48 R223 4.7K/NA 

I2CFAST 

47 

CARDBUSENA 

72 

XTPA0M 

73 

XTPA0P 

71 

XTPB0P 

70 

XTPB0M 

80 

XTPA1P 

79 

XTPA1M 

78 

XTPB1P 

77 

XTPB1M 

87 

XTPA2P 

86 

XTPA2M 

85 

XTPB2P 

84 

XTPB2M 

74 TPBIAS 

XTPBIAS0 

81 

XTPBIAS1 

88 

XTPBIAS2 

63 1 2 

XCPS 

66 R218 1K 

XRES 

60 XI 

XI 

61 XO 

XO 

29 EECS 

EECS/EEAUTO# 

30 EEDO 

EEDO 

31 EEDI 

EEDI/SDA 

32 EECK 

EECK/SCL/EEFAST 

37 

PME# 

43 

MODE0 

42 

MODE1 

38 

NC0 

40 

NC1 

44 

NC2 

45 

NC3 

51 

NC4 

56 

NC5 

57 

NC6 

67 

NC7 

VT6307L 

PQFP128A_0.5MM 

+3V 

TPA- 

TPA+ 

TPB+ 

TPB- 

R599 

C601 

6.34K 

47P 

0603 

0603 

1% 

10% 

GND 

PCI_PME# 9,10,16,17,18,20 

TPA- 22 

TPA+ 22 

TPB+ 22 

TPB- 22 

R593 

R592 R590 

R591 

54.9 

54.9 54.9 

54.9 

0603 

0603 0603 

0603 

1% 

1% 

1% 

1% 

TPBIAS 

R598 

C598 

C597 

4.99K 

270P 

0.33U 

0603 

0603 

0603 

1% 

10% 

16V 

GND GND 

Configuration Straps 

I2CEEENA I2C EEPROM. 

0: 4-wire EEPROM interface(Default) 

1: 2-wire I2C EEPROM interface using SCL/SDA 

I2CFAST I2C EEPROM Fast Mode 

EECS 

EECK 

EEDI 

EEDO 

L523 

1 2 

120Z/100M 

2012 

GND 

1394_AGND 

XI 

R220 

XO 

1 2 

1M 

0603 

X3 

1 2 

24.576MHZ 

C227 

C235 

10P 

10P 

0603 

0603 

5% 

5% 

GND GND 

+3V 

U10 

1 

8 

CS VCC 

2 

7 

SK NC1 

3 

6 

DI NC0 

C252 

4 5 

1U 

DO GND 

0603 

NM93C46 

SO8 

GND 

C 

2 

1 

2 

1 

2 

1 

2 

C242 

0.1U 

0603 

50V 

1 

2 

1 

2 

1 

2 

2 

1 

2 

C222 

0.1U 

0603 

50V 

1 

2 

8 

20 

33 

35 

102 

113 

114 

125 

VCC0 

VCC1 

VCC2 

VCC3 

VCC4 

VCC5 

VCC6 

VCC7 

C230 C238 

0.1U 0.1U 

0603 0603 

50V 50V 

65 

75 

89 

GND0 

GND1 

GND2 

GND3 

GND4 

GND5 

GND6 

GND7 

GND8 

GND9 

GND10 

1 

9 

16 

26 

34 

36 

94 

103 

111 

115 

121 

VCCARX0 

VCCARX1 

VCCARX2 

62 

76 

90 

GNDARX0 

GNDARX1 

GNDARX2 

64 

68 

82 

VCCATX0 

VCCATX1 

VCCATX2 

1394_AGND 

24 

39 

49 

VCCRAM 

VCCSUS[0] 

VCCSUS[1] 

1 

2 

GNDATX0 

GNDATX1 

GNDATX2 

GNDRAM 

GNDSUS[0] 

GNDSUS[1] 

59 

69 

83 

25 

41 

50 


GND 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

L21 

1 2 

120Z/100M 

2012 

1 

2 


1394_VCC 

Rev 

411675300001 03 


1 


1 

2 

1 

2

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

Place as close to VT6105LOM as possible. 

TEST MODE(0=Internal PHY test mode, 1=Normal mode) 

N-WAY enable(0=disable, 1=enable) 

GND_45 

Mount to enable Cable Detect. 

GND_45 

RJ45 

GND_45 

GND_45 

Pull high at EC side. 

Mount when use WOL function. 

STRAPPING 

IDSEL: AD18 

PCI REQ1# 

PCI GNT1# 

PCI INTE# 

VT6105L 

411675300001 03 


C 

16 29 


Title 

Size 

Document 

Number 

Rev 


AD19 

AD14 

RXIN- 

AD27 

AD2 

PJTX- 

PJ7 

LANTEST1 

AD15 

LANTEST1 

AD6 

AD18 

CBE#1 

EESK 

AD3 

LAN_NWAY 

EECS 

AD21 

AD4 

EEDI 

PJRX+ 

AD28 

AD11 

CBE#0 

TXD- 

PJTX+ 

AD23 

AD30 

CBE#3 

AD31 

LAN_GPIO 

AD1 

LANTEST0 

CBE#[0..3] 

LAN_WAKE 

EEDO 

AD13 

AD7 

TXD- 

AD8 

PJRX- 

AD5 

CBE#2 

AD26 

LANTEST0 

PJRX+ 

EEDO 

LAN_WAKE 

PJ4 

AD25 

PJ7 

RXIN+ 

EECS 

AD17 

AD9 

LANX2 

LAN_GPIO 

TXD+ 

AD0 

AD20 

AD22 

AD16 

PJTX+ 

LANX1 

EEDI 

AD18 

PJTX- 

TXD+ 

AD12 

LANX1 

LAN_TEST 

PJRX- 

AD[0..31] 

PJ4 

EESK 

AD29 

LAN_TEST 

AD10 

LANX2 

LAN_NWAY 

AD24 

RXIN+ 

RXIN- 

+LAN_A2.5V 

+LAN_A2.5V 

GND 

LAN_GND 

LAN_GND 

GND 

+LAN_D2.5V 

+3V 

GND 

+LAN_A2.5V 

+3V_P 

+LAN_D2.5V 

LAN_GND 

+3V_P 

+LAN_D2.5V 

+2.5V_DDR 

GND 

LAN_GND 

+LAN_D3V 

GND 

+3V_P 

+LAN_A2.5V 

+LAN_D3V 

LAN_GND 

GND 

+LAN_A2.5V 

GND 

GND 

GND 

+3V_P 

+3V 

GND 

+LAN_A2.5V 

GND 

+3V_P 

GND 

+LAN_D2.5V 

+LAN_D3V 

GND 

+LAN_D3V 

R253 

10K 

0603 1 2 

U16 

NM93C46 

SO8 

1 

2 

3 

4 5 

6 

7 

8 

CS 

SK 

DI 

DO GND 

NC0 

NC1 

VCC 

C290 

1U 

0603 

1 

2 

R255 

10K 

0603 1 2 

C322 

0.1U 

50V 

0603 

1 

2 

C316 

0.1U 

16V 

0603 

1 2 

R298 

10K 

0603 

1 

2 

R246 

49.9 

0603 

1% 

1 

2 

JS503 

SHORT-SMT4 

1 2 

R285 

0/NA 

0603 

0603D_DFS 

1 2 

R250 

10K 

0603 1 2 

C287 

2.2U 

16V 

1206 

1 

2 

JO37 

1 2 

C273 

0.1U 

50V 

0603 

1 

2 

R244 

49.9 

0603 

1% 

1 

2 

C311 

0.1U 

16V 

0603 

1 

2 

L34 

120Z/100M 

2012 

1 2 

C308 

0.1U 

50V 

0603 

1 

2 

R224 

75 

0603 

1% 

1 

2 

R259 

6.04K 

0603 

1% 

1 

2 

JO36 

1 2 

R229 

75 

0603 

1% 

1 

2 

R254 

10K 

0603 

1 2 

R230 

75 

0603 

1% 

1 

2 

JS3 

SHORT-SMT4 

1 2 

JO34 

1 2 

J515 

8PX1/1.016MM 

291000810806 

CONN_PJS-AST_8 

1 

2 

3 

4 

5 

6 

7 

8 

GND1 

GND2 

GND3 

GND4 

1 

2 

3 

4 

5 

6 

7 

8 

GND1 

GND2 

GND3 

GND4 

C313 

0.1U 

50V 

0603 

1 

2 

U11 

LF-H80P 

SOX16 

7 

6 

8 

10 

11 

9 

1 

3 

2 

16 

14 

15 

4 

5 

12 

13 

TD+ 

TDC 

TD1- 

TX+ 

TXC 

TX- 

RD+ 

RDC 

RD- 

RX+ 

RXC 

RX- 

NC0 

NC1 

NC2 

NC3 

X4 25MHZTXC7X5 

1 3 

2 

4 

C293 

2.2U 

16V 

1206 

1 

2 

JO35 

1 2 

C282 

0.1U 

50V 

0603 

1 

2 

C275 

0.1U 

50V 

0603 

1 

2 

R530 

0/NA 

0805C_DFS 

1 2 

R316 

0/NA 

0603 

1 2 

JS7 

SHORT-SMT4 

1 2 

C296 

0.1U 

50V 

0603 

1 

2 

Q20 

DTC144WK 

1 

2 

3 

JS504 

SHORT-SMT4 

1 2 

TP522 

1 

C288 

0.1U 

50V 

0603 

1 

2 

R703 

10K/NA 

0603 

1 

2 

JO38 

1 2 

JS508 

SHORT-SMT4 

1 2 

R317 

4.7K 

0603 

1 

2 

R239 

0/NA 

0603D_DFS 

1 

2 

JS505 

SHORT-SMT4 

1 2 

Q24 

DTC144WK 

1 

2 

3 

C286 

0.1U 

50V 

0603 

1 

2 

C281 

0.1U 

50V 

0603 

1 

2 

R245 

49.9 

0603 

1% 

1 

2 

C233 

1000P 

2KV 

1806 

10% 

1 

2 

JO40 

1 2 

R315 

0/NA 

0603D_DFS 

1 2 

R243 

49.9 

0603 

1% 

1 

2 

JS506 

SHORT-SMT4 

1 2 

R369 

10K/NA 

0603 

1 

2 

L28 

120Z/100M 

1608 

1 2 

C304 

0.1U 

50V 

0603 

1 

2 

C279 

22P 

0603 

5% 

1 

2 

C321 

0.1U 

50V 

0603 

1 

2 

L27 

PLP3216S 

1 

4 

2 

3 

C298 

0.1U 

50V 

0603 

1 

2 

R303 

2.2 

0603 

1 2 

R257 

1M/NA 

0603D 

1 2 

R262 

100K/NA 

0603 

1 

2 

TP521 

1 

R249 

10K 

0603 1 2 

L33 

120Z/100M 

2012 

1 2 

C276 

0.1U 

50V 

0603 

1 

2 

R282 

0/NA 

0603 

1 2 

U15 

VT6105-LOM 

PQFP128A_0.4MM 

19 

15 

92 

99 

42 

102 

107 

4 

17 

117 

114 

87 

90 

89 

88 

118 

113 

50 

23 

22 

74 

75 

76 

77 

78 

79 

80 

83 

59 

60 

61 

62 

63 

101 

100 

49 

111 

3 

16 

28 

40 

56 

67 

81 

82 

47 

46 

45 

44 

39 

38 

37 

36 

34 

33 

32 

30 

29 

27 

26 

25 

13 

12 

11 

10 

8 

7 

6 

5 

1 

128 

127 

126 

124 

123 

122 

121 

35 

24 

14 

2 

43 

120 

91 

97 

103 

106 

96 

20 

31 

41 

9 

125 

116 

110 

68 

55 

48 

93 

54 

57 

58 

21 

18 

84 

115 

98 

94 

95 

105 

104 

109 

108 

85 

86 

112 

119 

53 

52 

51 

64 

65 

66 

69 

70 

71 

72 

73 

DEVSEL# 

FRAME# 

GNDA5 

GNDAREXT 

GNDRAM 

GNDRX 

GNDTX 

IDSEL 

IRTY# 

GNT# 

PCIRST# 

LED3 

LED0 

LED1 

LED2 

REQ# 

INTA# 

ECS 

PAR 

PERR# 

NC11 

NC12 

NC13 

NC14 

NC15 

NC16 

NC17 

NC18 

NC19 

NC20 

NC21 

NC22 

NC23 

NC24 

NC25 

VCC25_0 

VCC25_1 

VCC33_0 

VCC33_1 

VCC33_2 

VCC33_3 

VCC33_4 

VCC33_5 

GND 

VCC33_7 

AD0 

AD1 

AD2 

AD3 

AD4 

AD5 

AD6 

AD7 

AD8 

AD9 

AD10 

AD11 

AD12 

AD13 

AD14 

AD15 

AD16 

AD17 

AD18 

AD19 

AD20 

AD21 

AD22 

AD23 

AD24 

AD25 

AD26 

AD27 

AD28 

AD29 

AD30 

AD31 

CBE0# 

CBE1# 

CBE2# 

CBE3# 

VCCRAM 

VCC 

VCCA 

VCCREXT 

VCCRX 

VCCTX 

VCCXTAL 

GND0 

GND1 

GND2 

GND3 

GND4 

GND5 

GND6 

GND7 

GND8 

GND9 

GNDA1 

EDO 

EDI 

ECK 

STOP# 

TRDY# 

GPIO 

PCICLK 

REXT 

X0 

X1 

RXM 

RXP 

TXM 

TXP 

TESTM0 

TESTM1 

WOL 

PME# 

NC0 

NC1 

NC2 

NC3 

NC4 

NC5 

NC6 

NC7 

NC8 

NC9 

NC10 

R222 

75 

0603 

1% 

1 

2 

L26 

PLP3216S 

1 

4 

2 

3 

C284 

22P 

0603 

5% 

1 

2 

LAN_PCIRST# 

9 

PCI_STOP# 

9,15,17,18 

PCI_TRDY# 

9,15,17,18 

PCI_REQ1# 

9 

PCI_GNT1# 

9 

PCI_IRDY# 

9,15,17,18 

EC_RI# 20 

INT_PIRQE# 

9 

PCI_PAR 

9,15,17,18 

CARD_RI# 

18 

PCI_DEVSEL# 

9,15,17,18 

PCI_FRAME# 

9,15,17,18 

ICH_RI# 9 

AD[0..31] 

9,15,17,18 

PCICLK_LAN 

4 

PCI_PME# 

9,10,15,17,18,20 

PCI_PERR# 

9,15,17,18 

CBE#[0..3] 9,15,17,18 


5 

5 

4 

4 

3 

10 USBP0- 

J510 

B 

L39 

+VCC_USB0 1 

2 

3 

4 

1 

2 

3 

4 

GND GND 

GND 

B 

1 2 

JO5 

USB_GND 

USB_GND USB_GND 

JS1 

SHORT-SMT4 GND 

+VCC_USB1 

1 

2 

3 

4 

GND1 

GND2 

GND3 

GND4 

J512 

1 

2 

3 

4 

GND1 

GND2 

GND3 

GND4 

USB/4P/FM 

ALLTOP 

C10713-10409 

1 2 

+5V 

CBE#[0..3] 

AD[0..31] 

Mini PCI 

J520 

IDSEL: AD17 

1 

2 

D PCI REQ3# 

3 

5 

4 

6 

D 

PCI GNT3# 

PCI INTD# INTF# 

INTEL_PD# 

7 

9 

11 

13 

8 

10 

12 

14 

+3V 

15 

16 

17 

19 

21 

23 

25 

27 

18 

20 

22 

24 

26 

28 

R514 0/NA 

1 2 

0603D_DFS 

+3V 

C49 

10P/NA 

0603 

AD31 

AD29 

AD27 

AD25 

CBE#3 

AD23 

29 

31 

33 

35 

37 

39 

41 

43 

45 

47 

30 

32 

34 

36 

38 

40 

42 

44 

46 

48 

AD30 

AD28 

AD26 

AD24 

AD17 

AD21 

AD19 

AD17 

CBE#2 

49 

51 

53 

55 

57 

59 

50 

52 

54 

56 

58 

60 

AD22 

AD20 

AD18 

AD16 

61 

63 

65 

67 

69 

62 

64 

66 

68 

70 

C 

+5V_P 

1 2 

R212 0/NA 

0805C_DFS 

U8 

3 

VIN0 

4 

VIN1 

1 

VOUT0 

5 

VOUT1 

RT9701-CBL 

SOT25 

+ 

+VCC_USB0 

+VCC_USB1 

Change to 

330u POS-CAP 

CBE#1 

AD14 

AD12 

AD10 

AD8 

AD7 

AD5 

AD3 

AD1 

71 

73 

75 

77 

79 

81 

83 

85 

87 

89 

91 

93 

95 

97 

99 

101 

72 

74 

76 

78 

80 

82 

84 

86 

88 

90 

92 

94 

96 

98 

100 

102 

CBE#0 

AD15 

AD13 

AD11 

AD9 

AD6 

AD4 

AD2 

AD0 

INTEL_PD# 

+3V 

1 2 

R146 33 

C 

GND 

103 

104 

+5V 

105 

106 

GND GND 

107 

109 

111 

113 

115 

108 

110 

112 

114 

116 

R348 

330 

0603 

117 

118 

119 

120 

GND 

121 

123 

122 

124 

D22 

C679 

9,15,16,18 CBE#[0..3] 

9,15,16,18 AD[0..31] 

0/NA 

0603D_DFS 

1 2 

R535 

4 PCICLK_MINIPCI 

9,18 INT_PIRQF# 

1 2 

R41 

0/NA 

0603D_DFS 

INT_PIRQD# 9 

MINIPCI_PCIRST# 9 

R519 

10K 

0603 

9 PCI_REQ3# 

PCI_GNT3# 9 

R529 100 0603 

1 2 

PCI_PME# 9,10,15,16,18,20 

C108 

2.2U 

1206 

16V 

C94 

0.1U 

0603 

50V 

C60 

0.1U 

0603 

50V 

C532 

0.1U 

0603 

50V 

C516 

0.1U 

0603 

50V 

C506 

0.1U 

0603 

50V 

C504 

0.1U 

0603 

50V 

C25 

0.1U 

0603 

50V 

PCI_PAR 9,15,16,18 

9,15,16,18 PCI_IRDY# 

9,10,18,19 PCLKRUN# 

9,18 PCI_SERR# 

PCI_FRAME# 9,15,16,18 

PCI_TRDY# 9,15,16,18 

PCI_STOP# 9,15,16,18 

C187 

1U 

0603 

10 USBOC0# 

R204 

33K 

0603 

330U 

7343 

6.3V 

9,15,16,18 PCI_PERR# 

PCI_DEVSEL# 9,15,16,18 

R126 1 2 10K 

0603 

WIRELESS_PD# 10 

C166 

1000P 

0603 

R205 

47K 

0603 

MINIPCI_ACT# 10 

1 

2 

10 USBP0+ 

10 USBP1- 

10 USBP1+ 

1 

2 

1 

2 

1 

2 

2 1 

3 4 

GND 

2 

90Z/100M 

CHOKE_ACM2012 

2 1 

1 

2 

3 4 

1 

2 

L40 

90Z/100M 

CHOKE_ACM2012 

1 

2 

1 2 

JO33 

1 2 

1 2 

1 

2 

1 

2 

JO4 

JO6 

1 

2 

1 

2 

1 

2 

GND1 

GND2 

GND3 

GND4 

GND1 

GND2 

GND3 

GND4 

1 

2 

USB/4P/FM 

ALLTOP 

C10713-10409 

1 2 

1 

2 

KO0 

1 2 

JO519 

GND 

A JS2 

A 

SHORT-SMT4 

JO520 

JO527 

JO517 

JO526 

JO518 

JO523 

USB_GND 

USB_GND USB_GND 

GND 

3 

GND1 

GND2 

KI0 

GND 

KI0 20 

KO0 1 

3 

SW503 

2 

4 

KI1 

KI1 20 

KO0 1 

3 

SW507 

2 

4 

KI2 

KI2 20 

5 

5 

GND 

KO1 1 

SW506 

2 KI0 

KO1 1 

SW505 

2 KI1 KO1 1 

SW502 

2 KI2 

3 

4 

3 

4 

3 

4 

5 

5 

5 

1 2 

SW504 

1 

3 

5 

12V/50MA 

PT-036-B2F 

12V/50MA 

PT-036-B2F 


20,21 KO0 

20,21 KO1 

2 

4 

1 2 

1 2 

124P/0.8MM/H6 

SPEED 

B27-102-0038 

JO525 

JO522 

GND GND 

GND 

GND 

1 2 

1 2 

+3V 

12V/50MA 

PT-036-B2F 

12V/50MA 

PT-036-B2F 

JS501 

SHORT-SMT3 

1 2 

JO524 

1 2 

1 2 

GND 

+3V 

2 

2 

G 

1 2 

JO521 

1 2 

1 

A2 

DK 

S 

GND 

CL-190G 

D Q14 

S 

2N7002 

12V/50MA 

PT-036-B2F 

12V/50MA 

PT-036-B2F 

1 

2 

1 2 

JO528 

1 2 

GND 

GND GND 

Title 

Size 

C 

Document 

Number 

1 


Rev 

411675300001 03 


1 

Sheet 17 of 29

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

(43K) 

ENE CP2211:286302211002 

Multi Function pin need pull up. 

IDSEL: AD20 

PCI REQ2# 

PCI GNT2# 

PCI INTB# INTF# 

CB710 

411675300001 03 


C 

18 29 


Title 

Size 

Document 

Number 

Rev 


AD0 

AD1 

AD3 

AD2 

AD5 

AD4 

AD7 

AD6 

AD13 

AD9 

AD8 

AD12 

AD14 

AD15 

AD11 

AD10 

AD21 

AD29 

AD28 

AD17 

AD16 

AD30 

AD24 

AD25 

AD20 

AD27 

AD26 

AD22 

AD23 

AD31 

AD19 

AD18 

AD[0..31] 

CBE#0 

CBE#1 

CBE#2 

CBE#3 

CBE#[0..3] 

CAD0 

CAD1 

CAD3 

CAD2 

CAD5 

CAD4 

CAD7 

CAD6 

CAD12 

CAD15 

CAD9 

CAD8 

CAD13 

CAD11 

CAD10 

CAD14 

CAD28 

CAD20 

CAD24 

CAD25 

CAD23 

CAD26 

CAD17 

CAD16 

CAD21 

CAD19 

CAD31 

CAD30 

CAD18 

CAD27 

CAD29 

CAD22 

CAD7 

CAD28 

CCLK 

CAD2 

CAD5 

CPERR# 

CAD25 

CAD24 

R2_A18 

CCBE2# 

R2_D2 

CINT# 

CAD20 

CAD30 

CCLKRUN# 

CAD13 

CSTOP# 

CAD11 

CAD0 

R2_D14 

CAD15 

CAD31 

CAD27 

CCD2# 

CDEVSEL# 

CSERR# 

CAD10 

CRST# 

CAD12 

CCBE1# 

CAD4 

CREQ# 

CBLOCK# 

CAD6 

CCBE0# 

CAD1 

CAD23 

CAD17 

CAD16 

CCBE3# 

CAD26 

CAD14 

CPAR 

CAD8 

CAUDIO 

CAD21 

CAD9 

CAD19 

CFRAME# 

CCD1# 

CAD3 

CAD18 

CVS1 

CTRDY# 

CGNT# 

CSTSCHG 

CAD29 

CIRDY# 

CVS2 

CAD22 

CCD1# 

CCD2# 

CVS2 

CVS1 

CCBE1# 

CCBE2# 

CCBE0# 

CCBE3# 

R2_D2 

CSTOP# 

CTRDY# 

CPAR 

R2_D14 

CDEVSEL# 

R2_A18 

CBLOCK# 

CSERR# 

CIRDY# 

CPERR# 

CSTSCHG 

CINT# 

CGNT# 

CAUDIO 

CREQ# 

CRST# 

CFRAME# 

CCLK 

CCLKRUN# 

CB_PCIRST# 

VPPD1 

VPPD0 

VCC3_EN# 

VCC5_EN# 

CARD_ACT 

SD3 

SD2 

SD1 

SD0 

SM_ALE 

SM_SD4 

MS_INS# 

SM_SD7 

SM_WE# 

SM_CLE 

SM_CE# 

SD3 

SM_RE# 

SM_SD3 

SM_WPD# 

SM_CD# 

MS_BS 

SD_CMD 

SD0 

SD2 

SM_SD2 

SD1 

SM_LVD 

SDCD# 

SD_CLK 

MS_SDIO 

SM_R/B# 

SD_WP# 

SM_SD6 

SM_WP# 

MS_SCLK 

SM_SD1 

SM_SD0 

SM_SD5 

MS_PWREN# 

SD_PWREN# 

SM_WE# 

SD0 

SM_R/B# 

SM_LVD 

SDCD# 

MS_INS# 

SD1 

SD_CMD 

SD3 

SM_CD# 

SM_RE# 

SM_CE# 

MS_BS 

MS_SDIO 

SM_WPD# 

SD2 

SD_WP# 

MS_SCLK 

SD_CLK 

SD_PWREN# 

SD_CLK1 

SD_CMD 

SD_WP# 

SDCD# 

SD_LED# 

MS_CLK1 

SD_CLK1 SD_CLK 

MS_SCLK 

SM_SD7 

SM_SD6 

SM_SD4 

SM_SD5 

SM_SD0 

SM_SD2 

SM_SD1 

SM_SD3 

SM_WE# 

SM_LVD 

SM_ALE 

SM_CLE 

SM_LED# 

SM_CD# 

SM_RE# 

SM_R/B# 

SM_WPD# 

SM_WP# 

SM_PWR3EN# 

SM_CE# 

SM_PWR5EN# 

MS_PWREN# 

MS_CLK1 

MS_BS 

MS_LED# 

MS_INS# 

MS_SDIO 

SC_PWR5EN# 

SC_PWR3EN# 

CRST# 

CCLKRUN# 

VCC3_EN# VPPD0 

VPPD1 

VCC5_EN# 

CARD_MF1 

CARD_RI# 

CARD_ACT 

SM_PWR3EN# 

CARD_MF1 

SERIRQ 

AD20 

CAD11 

GND 

GND 

+VPPOUT 

+CARD_VCC 

+VPPOUT 

GND 

+3V 

+CARD_VCC 

GND 

GND 

+SDVDD 

GND 

+MSVDD 

GND 

+SDVDD 

GND 

+SMVDD 

+SDVDD 

+MSVDD 

+SDVDD 

GND 

+SMVDD 

+3V 

GND 

GND 

GND 

GND 

GND 

GND 

+3V 

+CARD_VCC 

+5V 

GND 

+CARD_VCC 

GND 

+3V 

GND 

GND GND 

+3V 

+VPPOUT 

+3V 

GND 

+3V 

+3V 

+3V 

C301 

1U 

1 

2 

R295 43K 0603 

1 2 

R321 10K/NA 

1 2 

R266 4.3K/NA 

1 2 

R270 

10 

0603 

1 2 

R300 

0/NA 

0805C_DFS 

1 

2 

R260 0/NA 

0603D_DFS 

1 2 

J517 

0.6/H7.5/68P 

P2P2601-220 

TAI-SOL 

G1 

G2 

G3 

G4 

G5 

G6 

G8 

G7 

GND1 

GND2 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

33 

34 

35 

36 

37 

38 

39 

40 

41 

42 

43 

44 

45 

46 

47 

48 

49 

50 

51 

52 

53 

54 

55 

56 

57 

58 

59 

60 

61 

62 

63 

64 

65 

66 

67 

68 

G1 

G2 

G3 

G4 

G5 

G6 

G8 

G7 

GND1 

GND2 

GND[0] 

CAD0 

CAD1 

CAD3 

CAD5 

CAD7 

CCBE0# 

CAD9 

CAD11 

CAD12 

CAD14 

CCBE1# 

CPAR 

CPERR# 

CGNT# 

CINT# 

VCC0 

VPP1 

CCLK 

CIRDY# 

CCBE2# 

CAD18 

CAD20 

CAD21 

CAD22 

CAD23 

CAD24 

CAD25 

CAD26 

CAD27 

CAD29 

RFU[0] 

CCLKRUN# 

GND[1] 

GND[2] 

CCD1# 

CAD2 

CAD4 

CAD6 

RFU[1] 

CAD8 

CAD10 

CVS1 

CAD13 

CAD15 

CAD16 

RFU[2] 

CBLOCK# 

CSTOP# 

CDEVSEL# 

VCC1 

VPP2 

CTRDY# 

CFRAME# 

CAD17 

CAD19 

CVS2 

CRST# 

CSERR# 

CREQ# 

CCBE3# 

CAUDIO 

CSTSCHG 

CAD28 

CAD30 

CAD31 

CCD2# 

GND[3] 

C297 

0.1U 

50V 

0603 

1 

2 

R296 43K 0603 

1 2 

C309 

0.1U 

50V 

0603 

1 

2 

C335 

2.2U 

16V 

1206 

1 

2 

C307 

0.1U 

50V 

0603 

1 

2 

R289 43K 0603 

1 2 

R339 

10K 

0603 

1 

2 

C306 

0.1U 

50V 

0603 

1 

2 

R263 4.3K/NA 

1 2 

U21 

TPS2211A SSOP16 

286302211002 

1 

2 

3 

4 

5 

6 

7 

8 

16 

15 

14 

13 

12 

11 

10 

9 

VCCD0 

VCCD1 

3.3VA 

3.3VB 

5VA 

5VB 

GND 

OC 

SHDN 

VDDP0 

VDDP1 

AVCCA 

AVCCB 

AVCCC 

AVPP 

12V 

R286 43K 0603 

1 2 

R264 0/NA 

1 2 

C300 

1U 

1 

2 

J516 

37P/H6.75/SMT 

TAI-SOL 

P5S2E920 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

33 

34 

35 

36 

37 

GND[0] 

SW-CD1 

SW-WP1 

DAT1 

DAT0 

CLK 

CMD 

DTA3 

DAT2 

VCC[0] 

CD 

D4 

D3 

D5 

D2 

D6 

D1 

D7 

D0 

LVD 

WP-IN 

WE 

BSY 

ALE 

RE 

CLE 

CE 

SW-WP2 

SW-CD2 

VCC[1] 

BS 

SDIO 

RESERVED1 

INS 

RESERVED2 

SCLK 

GND[1] 

C337 

1U 

0603 

1 

2 

R332 

43K 

0603 

1 

2 

R310 

0 

0805C 

1 

2 

C291 

0.1U 

50V 

0603 

1 

2 

R342 

10K 

0603 

1 

2 

C320 

0.1U 

50V 

0603 

1 

2 R319 10K/NA 

1 2 

R294 43K 0603 

1 2 

R274 43K 0603 

1 2 

C303 

0.1U 

50V 

0603 

1 

2 

D 

S G 

Q22 

SI2301DS 

G 

D 

S 

C334 

0.1U 

50V 

0603 

1 

2 

R258 

43K 

0603 

1 

2 

C336 

0.1U 

50V 

0603 

1 

2 

R322 10K 

1 2 

R292 

100K 

0603 

1 

2 

R335 0/NA 

0603D_DFS 

1 2 

R299 

0/NA 

0805C_DFS 

1 

2 

C305 

0.1U 

50V 

0603 

1 

2 

R269 43K 0603 

1 2 

R279 

10 

0603 

1 2 

C317 

0.1U 

50V 

0603 

1 

2 

R337 

0/NA 

0603D_DFS 

1 2 

R318 

33 

0603 

1 

2 

R320 10K 

1 2 

R293 8.2K 0603 

1 2 

R267 4.3K/NA 

1 2 

C289 

0.1U 

50V 

0603 

1 

2 

R273 43K 0603 

1 2 

R261 

0/NA 

0603D_DFS 

1 2 

R280 4.7K 

1 2 

R333 

10K 

0603 

1 

2 

C299 

10P 

0603 

5% 

1 

2 

R275 8.2K 0603 

1 2 

R272 8.2K 0603 

1 2 

R312 10K/NA 

1 2 

R288 43K/NA 0603 

1 2 

U17 

CB710 

BGA_GHK_209 

H5 

G1 

G3 

H6 

F1 

G5 

F2 

E1 

G6 

F5 

E3 

C12 

A4 

E6 

B5 

F6 

B8 

A8 

E9 

F9 

B9 

A9 

F10 

E10 

F11 

E13 

C11 

B11 

A12 

B12 

E12 

A13 

F15 

E17 

A16 

C15 

E14 

F13 

B15 

E19 

A10 

F14 

F17 

G15 

C14 

D19 

A14 

C13 

B13 

C10 

F8 

A7 

B7 

C7 

F7 

A6 

B6 

C6 

E2 

A5 

C8 

A15 

R8 

W7 

V7 

W6 

V6 

U6 

V5 

U5 

N1 

M3 

L1 

M1 

T1 

N3 

P1 

P5 

P6 

M6 

N2 

N6 

N5 

R1 

R2 

R3 

W4 

R6 

W10 

U10 

P10 

H2 

J1 

J3 

K1 

K3 

V10 

R10 

W11 

H1 

J2 

J6 

K2 

K5 

H3 

R9 

K6 

L2 

L6 

L5 

M2 

P3 

U9 

V9 

W9 

W8 

V8 

U8 

P7 

P8 

R7 

W5 

J19 

K14 

K15 

K19 

L15 

L17 

L19 

M15 

W16 

R14 

W14 

P14 

N18 

R17 

N14 

M14 

P18 

U15 

T19 

P15 

R18 

P17 

P19 

N17 

N19 

M18 

H14 

G18 

G14 

U11 

R11 

U12 

R12 

V13 

H15 

G17 

F19 

P11 

V12 

P12 

W13 

U13 

V11 

H17 

P13 

R13 

J18 

M19 

U14 

W15 

V15 

R19 

L18 

H18 

H19 

J15 

J14 

J17 

K17 

L14 

D1 

E11 

F3 

L3 

U7 

W12 

N15 

G19 

B14 

A11 

C9 

E7 

F18 

M17 

M5 

G2 

J5 

P2 

P9 

V14 

K18 

E18 

F12 

B10 

E8 

C5 

E5 

AD0 

AD1 

AD2 

AD3 

AD4 

AD5 

AD6 

AD7 

AD8 

AD9 

AD10 

AD11 

AD12 

AD13 

AD14 

AD15 

AD16 

AD17 

AD18 

AD19 

AD20 

AD21 

AD22 

AD23 

AD24 

AD25 

AD26 

AD27 

AD28 

AD29 

AD30 

AD31 

MFUNC0 

MFUNC1 

MFUNC2 

MFUNC3 

MFUNC4 

MFUNC5 

MFUNC6 

VCCD0# 

PCLK 

VCCD1# 

VPPD2 

SPKROUT 

RI_OUT#PME# 

SUSPEND# 

PRST# 

GNT# 

REQ# 

IDSEL 

FRAME# 

IRDY# 

TRDY# 

DEVSEL# 

STOP# 

PERR# 

SERR# 

PAR 

C/BE0# 

C/BE1# 

C/BE2# 

C/BE3# 

A0/CAD26 

A1/CAD25 

A2/CAD24 

A3/CAD23 

A4/CAD22 

A5/CAD21 

A6/CAD20 

A7/CAD18 

A8/CCBE1# 

A9/CAD14 

A10/CAD9 

A11/CAD12 

A12/CCBE2# 

A13/CPAR 

A14/CPERR# 

A15/CIRDY# 

A16/CCLK 

A17/CAD16 

A18/RSVD (R_A18) 

A19/CBLOCK# 

A20/CSTOP# 

A21/CDEVSEL# 

A22/CTRDY# 

A23/CFRAME# 

A24/CAD17 

A25/CAD19 

D0/CAD27 

D1/CAD29 

D2/RSVD (R_D2) 

D3/CAD0 

D4/CAD1 

D5/CAD3 

D6/CAD5 

D7/CAD7 

D8/CAD28 

D9/CAD30 

D10/CAD31 

D11/CAD2 

D12/CAD4 

D13/CAD6 

D14/RSVD (R_D14) 

D15/CAD8 

CD1#/CCD1# 

CD2#/CCD2# 

CE1#/CCBE0# 

CE2#/CAD10 

OE#/CAD11 

IORD#/CAD13 

IOWR#/CAD15 

WE#/CGNT# 

WP/CCLKRUN# 

BVD1/CSTSCHG 

BVD2/CAUDIO 

WAIT#/CSERR# 

READY/CINT# 

VS1#/CVS1 

VS2#/CVS2 

REG#/CCBE3# 

INPACK/CREQ# 

RESET/CRST# 

SM_ALE 

SM_R/B# 

SM_WE# 

SM_LVD 

SM_D7 

SM_D1 

SM_D2 

SM_D4 

SD_DAT2 

SD_CMD 

SD_LED# 

SD_CLK 

SC_OC# 

SC_CLK 

VCC_SC 

SC_LED# 

SC_PWR3EN# 

SD_DAT3 

SC_IO 

SC_RST# 

SC_C4 

GND5 

SC_CD# 

GPIO9 

SM_CD# 

SM_D3 

GPIO8 

GPIO6 

IRQSER 

GPIO10 

MS_SDIO 

MS_SCLK 

MS_LED# 

SD_WP 

GPIO7 

GPIO5 

VPPD0 

MS_BS 

MS_INS# 

MS_PWREN# 

MS_CLKIN 

SD_CD# 

GPIO11 

SM_LED# 

SD_PWREN# 

GND4 

SM_RE# 

SM_D5 

SD_DAT1 

SD_DAT0 

VCC_SD 

SC_C8 

SM_D6 

SM_WPD# 

SM_PWR3EN# 

SM_PWR5EN# 

SM_CE# 

SM_CLE 

SM_WP# 

SM_D0 

VCC1 

VCC9 

VCC2 

VCC3 

VCC4 

VCC5 

SC_PWR5EN# 

VCC7 

VCC8 

G_RST 

VCC10 

VCC11 

VPPD1 

VCC6 

VCCA 

GND0 

GND1 

GND2 

GND3 

SD_CLKIN 

GND6 

GND7 

GND8 

GND9 

GND10 

GND11 

NC 

R287 43K 0603 

1 2 

R290 43K 0603 

1 2 

C330 

0.1U 

50V 

0603 

1 

2 

R271 43K 0603 

1 2 

C302 

10P 

0603 

5% 

1 

2 

R276 43K 0603 

1 2 

R278 43K 0603 

1 2 

R268 43K 0603 

1 2 

R334 

0/NA 

0603D_DFS 

1 

2 

C314 

0.1U 

50V 

0603 

1 

2 

R277 43K 0603 

1 2 

AD[0..31] 

9,15,16,17 

PCI_FRAME# 

9,15,16,17 

PCI_IRDY# 

9,15,16,17 

PCI_TRDY# 

9,15,16,17 

PCI_DEVSEL# 

9,15,16,17 

PCI_PAR 

9,15,16,17 

PCI_STOP# 

9,15,16,17 

PCI_PERR# 

9,15,16,17 

PCI_SERR# 

9,17 

CBE#[0..3] 

9,15,16,17 

SERIRQ 

9,10,19 

PCICLK_CARD 

4 

PCI_GNT2# 

9 

CB_PCIRST# 

9 

PCI_REQ2# 

9 

CARDSPK# 

12 

SUSB# 

3,4,9,20,21,22,26,28,29 

PCI_PME# 

9,10,15,16,17,20 

PCLKRUN# 

9,10,17,19 

INT_PIRQB# 

9 

INT_PIRQF# 

9,17 

CARD_RI# 

16 

SM_LED# 21 

MS_LED# 21 

SD_LED# 21 


5 

5 

4 

4 

3 

U510 

20,21 SA[0..17] 

SA0 

SA1 

9 LAD[0..3] 

LAD[0..3] 

C 

XSTB# 

SD0 

SD1 

SD2 

SD3 

SD4 

SD5 

SD6 

SD7 

R659 

10K 

0603 

SA2 

SA3 

SA4 

SA5 

SA6 

SA7 

SA8 

SA9 

SA10 

SA11 

SA12 

SA13 

SA14 

SA15 

SA16 

SA17 

U512 

3 

2 SA4 

D0 Q0 

4 

5 SA5 

D1 Q1 

7 

6 SA6 

D2 Q2 

8 

9 SA7 

D3 Q3 

13 

12 SA8 

D4 Q4 

14 

15 SA9 

D5 Q5 

17 

16 SA10 

D6 Q6 

18 

19 SA11 

D7 Q7 

1 

20 

OC VCC 

11 

10 

G GND 

74AHC373_V TSSOP20 

+3V 

C662 

0.1U 

0603 

50V 

4 PCICLK_LPC 

9 LPC_PCIRST# 

9 LFRAME# 

9 LDRQ0# 

0/NA 

9 SUS_STAT# 

1 

0603D_DFS 

9,10,17,18 PCLKRUN# 

9,10,18 SERIRQ 

4 48M_SUPERIO 

20,21 IRQ1 

20,21 IRQ12 

20,21 IOR# 

20,21 IOW# 

21 SA18 

21 SA19 

LAD0 

LAD1 

LAD2 

LAD3 

2 R656 LPCPD# 

PCLKRUN# 

SIO_GPIO35 

DSKCHG# 

RDATA# 

WPROT# 

TRK0# 

INDEX# 

SA0 

SA1 

SA2 

SA3 

XSTB# 

XCNF2 

SA12 

SA13 

SA14 

SA15 

SA16 

SA17 

SA19 

15 

16 

17 

18 

8 

9 

12 

11 

7 

6 

10 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

33 

34 

95 

94 

93 

92 

91 

90 

87 

86 

85 

84 

83 

82 

81 

80 

79 

78 

77 

76 

75 

74 

LAD0 

LAD1 

LAD2 

LAD3 

LCLK 

LRESET# 

LFRAME# 

LDRQ# 

LPCPD# 

CLKRUN#/GPIO36 

SERIRQ 

SMI#/GPIO35 

CLKIN 

DSKCHG# 

HDSEL# 

RDATA# 

WP# 

TRK0# 

WGATE# 

WDATA# 

SETP# 

DIR# 

DR0# 

MTR0# 

INDEX# 

DENSEL 

DRATE0/IRSL2 

XA0/GPIO20 

XA1/GPIO21 

XA2/GPIO22 

XA3/GPIO23 

XA4/GPIO24/XSTB0# 

XA5/XSTB1#/XCNF2 

XA6/GPIO26/PRIQA/XSTB2# 

XA7/GPIO27/PIRQB 

XA8/GPIO30/PIRQC 

XA9/GPIO31/MTR1#/PIRQD 

XA10/GPIO32/XIORD#/MDRX 

XA11/GPIO33/XIOWR#/MDTX 

XA12/GPIO10/JOYABTN1/RI2# 

XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2 

XA14/GPIO12/JOYAY/CTS2# 

XA15/GPIO13/JOYBY/SOUT2 

XA16/GPIO14/JOYBX/RTS2# 

XA17/GPIO15/JOYAX/SIN2 

XA18/GPIO16/JOYBBTN0/DSR2# 

XA19/DCD2#/JOYABTN0/GPIO17 

PD0/INDEX# 

PD1/TRK0# 

PD2/WP# 

PD3/RDATA# 

PD4/DSKCHG# 

PD5/MSEN0 

PD6/DRATE0 

PD7/MSEN1 

PNF/XRDY 

SLCT/WGATE# 

PE/WDATA# 

BUSY_WAIT#/MTR1# 

ACK#/DR1# 

SLIN#_ASTRB#/STEP# 

INIT#/DIR# 

ERR#/HDSEL# 

AFD#_DSTRB#/DENSEL 

STB#_WRITE# 

DCD1# 

DSR1# 

SIN1 

RTS1#/TEST 

SOUT1/XCNF0 

CTS1# 

DTR1#_BOUT1/BADDR 

RI1# 

IRTX 

IRRX1 

IRRX2_IRSL0 

IRSL1 

IRSL3/PWUREQ# 

XD0/GPIO00/JOYABTN1 

XD1/GPIO01/JOYBBTN1 

XD2/GPIO02/JOYAY 

XD3/GPIO03/JOYBY 

XD4/GPIO04/JOYBX 

XD5/GPIO05/JOYAX 

XD6/GPIO06/JOYBBTN0 

XD7/GPIO07/JOYABTN0 

XWR#/XCNF1 

XRD#/GPIO34/WDO# 

XIOWR#/XCS1#/MTR1#/DRATE0 

XIORD#/GPIO37/IRSL2/DR1# 

XCS0#/DR1#/XDRY/GPIO25 

52 

50 

48 

46 

45 

44 

43 

42 

35 

36 

37 

40 

41 

47 

49 

51 

53 

54 

55 

56 

57 

58 

59 

60 

61 

62 

70 

69 

68 

67 

66 

3 

2 

1 

100 

99 

98 

97 

96 

4 

5 

73 

71 

72 

PIO_D0 

PIO_D1 

PIO_D2 

PIO_D3 

PIO_D4 

PIO_D5 

PIO_D6 

PIO_D7 

PIO_PNF# 

1 TP538 

1 TP539 

1 TP536 

1 TP537 

1 TP535 

1 TP534 

1 TP533 

1 TP532 

1 TP531 

COM1_DCD# 

COM1_DSR# 

COM1_RXD 

COM1_RTS# 

COM1_TXD 

COM1_CTS# 

COM1_DTR# 

COM1_RI# 

IRTX 

IRRX 

IRTX 22 

IRRX 22 

IRSEL0 22 

1 2 

IRSEL1 22 

1 2 

+3V 

R363 0/NA 0603D_DFS 

R641 10K/NA 

SD0 

SD[0..7] 20,21 

SD1 

SD2 

SD3 

SD4 

SD5 

SD6 

SD7 

MEMW# 21 

MEMR# 21 

R643 1 2 

MCCS# 20 


R642 1 2 

ROMCS# 20,21 


D37 D36 D35 D34 

D33 D32 D31 D30 

FDD pull high 

+5V 

RP507 

WPROT# 1 

10 

TRK0# 2 

9 INDEX# 

RDATA# 3 

8 

DSKCHG# 4 

7 

5 6 

4.7K*8 1206 

+3V 

LPCPD# 

1 2 R657 

0603 

10K 

XCNF2 XCNF2 

1 2 R647 

0603 

10K/NA 

XCNF1 MEMW# 

1 2 R658 

0603 

10K 

XCNF0 COM1_TXD 

1 2 R638 

C 

GND 

GND 

COM1_DTR# 

0603 

1 

10K 

2 R639 

PC87393 

PQFP100_0.5MM 

COM1_RI# 

PIO_PNF# 

0603 

1 

0603 

1 

10K/NA 

2 R640 

10K 

2 R325 

COM1_DSR# 

0603 

2 

10K 

1 R637 

0603 

10K 

GND 

B B 

ADM3311ARU/NA 

A TSSOP_SSOP28 

K 

A PIO_D5 

A 

RS232/SIO 

0.1U/NA 50V 

C686 1 2 0603 

0.1U/NA 50V 

C687 1 2 0603 

COM1_RTS# 

COM1_TXD 

COM1_DTR# 

COM1_DCD# 

COM1_DSR# 

COM1_RXD 

COM1_CTS# 

COM1_RI# 

+3V 

GND 

D/RTS# 

D/TXD 

D/DTR# 

D/DCD# 

D/DSR# 

D/RXD 

D/CTS# 

D/RI# 

0.1U/NA 

C689 1 2 

0603 

50V 

1 

2 

GND 

1 

1 

1 

1 

1 

1 

1 

1 

C685 

0.1U/NA 

0603 

50V 

TP526 

TP527 

TP529 

TP523 

TP524 

TP525 

TP528 

TP530 

1 

2 

GND 

GND 

C688 

0.1U/NA 

0603 

50V 

1 

2 

1 

2 

3 

Reserve for FWH 

+3V 

R655 

8.2K 

0603 

+3V 

TP25 

TP26 

TP27 

TP28 

TP29 

1 

1 

1 

1 

1 

LAD0 

LAD1 

LAD2 

LAD3 

LFRAME# 

RP504 

D 

SIO_GPIO35 

C647 

0.1U 

0603 

50V 

C661 

0.1U 

0603 

50V 

C667 

0.1U 

0603 

50V 

C626 

0.1U 

0603 

50V 

+3V 

PIO_D0 

PIO_D1 

PIO_D2 

PIO_D3 

1 

2 

3 

4 

5 

10 

9 

8 

7 

6 

PIO_D7 

PIO_D6 

PIO_D5 

PIO_D4 

+3V 

D 

1 

2 

1 

2 

1 

2 

6 

C1+ 

24 

C1- 

2 

C2+ 

23 

5 

SD 

EN/ 

3 

VCC 

GND 

27 

U515 

1 

V+ 

25 

V- 

4 

22 

C2- 

T1OUT 

21 

T2OUT 

20 

T3OUT 

7 

T1IN 

8 

T2IN 

9 19 

T3IN R1IN 

18 

R2IN 

10 

17 

R1OUT R3IN 

11 

16 

R2OUT R4IN 

12 

15 

R3OUT R5IN 

13 

R4OUT 

14 

28 

R5OUT C3+ 


26 

C3- 

1 

2 

C684 

0.1U/NA 

0603 

50V 

1 

2 

1 

2 

14 

39 

63 

88 

VDD0 

VDD1 

VDD2 

VDD3 

VSS0 

VSS1 

VSS2 

VSS3 

13 

38 

64 

89 

GND 

K 

K 

K 

K 

K 

K 

K 

D17 

CL-190G 

D16 

CL-190G 

D15 

CL-190G 

D14 

CL-190G 

D13 

CL-190G 

D12 

CL-190G 

D11 

CL-190G 

D10 

CL-190G 

A 

A 

A 

A 

A 

A 

A 

PIO_D0 

PIO_D1 

PIO_D2 

PIO_D3 

PIO_D4 

PIO_D6 

PIO_D7 

2 

2 

2 

X 

X 

0 

1 

0 

XCNF 

1 

0 

0 

1 

1 

1 

1 1 

1K*8/NA 1206 

Title 

Size 

C 

0 

0 

1 

0 

0 

1 

1 

NO BIOS 

1 

DESCRIPTION 

NORMAL MODE, XRDY DISABLED 

LATCH MODE, XA12-19, XRDY ENABLED 

LATCH MODE, GPIO10-17, XRDY ENABLED 

LATCH MODE, XA12-19, XRDY DISABLED 

LATCH MODE, GPIO10-17, XRDY DISABLED 

Document 

Number 


Rev 

411675300001 03 


1 

Sheet 19 of 29

FAN 

1 2 

5 

1 

2 

5 

1 

2 

Level Shift 

1 

2 

1 

2 

GND 

1 

2 

4 

4 

1 

2 

1 

2 

1 

2 

1 

2 

2 

R1 

1 

2 

3 

VDD3 

H8_AVREF 

U13 

1 

L544 

2 

3 

VCC 

RESET# 

2 

C278 

H8_VDDA 

R526 

0/NA 

GND_H8 JP_BEAD_DFS GND 

0.1U/NA 

0603 

R247 

100K/NA 

VDD5 

R609 

0603D_DFS 

0603D_DFS 

50V MAX809/NA 

SOT23N 

0603 

1 2 

VDD3 

GND 

VDD3 

27 RSMPWRON 

RSMPWRON 1 

R238 

1K 

2 

H8_PWRON 

L25 

120Z/100M 

1608 

C603 

0.1U 

0603 

50V 

0/NA 

0603D_DFS 

C602 

0.1U 

0603 

50V 

C680 

0.1U 

0603 

50V 

VDD5 

GND 

GND 

R242 

4.7K 

0603 

D 

J1 

0603 

R237 

20K 

0603 

GND 

GND_H8 

+3V_P 

RSMPWRON 1 3 

Q19 

RSMRST# 9 

D 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

KO0 

KO1 

KO2 

KO3 

KO4 

KO5 

KO6 

KO7 

KO8 

KO9 

KO10 

KO11 

KO12 

KO13 

KO14 

2 

2 

2 

2 

2 

2 

2 

2 

1 JO32 

2 

1 JO30 

2 

1 JO28 

2 

1 JO26 

2 

1 JO24 

2 

1 JO22 

2 

1 JO20 

2 

1 JO18 

1 JO31 

1 JO29 

1 JO27 

1 JO25 

1 JO23 

1 JO21 

1 JO19 

GND 

C607 

0.1U 

0603 

50V 

GND 

C611 C269 

0.1U 0.1U 

0603 0603 

50V 50V 

U504 

GND_H8 GND 

R39 

22 

0603 

C604 

0.1U 

0603 

50V 

GND_H8 

D9 

BAV70LT1 

BAT_TEMP 

BAT_VOLT 

C261 C260 

0.1U 0.1U 

0603 0603 

50V 50V 

GND_H8 

R235 1 

2.2K 

R236 1 

2.2K 

R35 1 

R612 1 

DTC144TKA 

2 BAT_T 

BAT_T 23 

0603 

2 BAT_V 

BAT_V 23 

0603 

2 0603 33 BAT_C 

BAT_D 

BAT_C 23 

2 0603 33 

BAT_D 23 

THRM_CLK 

THRM_DATA 

C277 

10U/NA 

1206 

10V 

GND 

C 

16 KO15 

2 

1 JO17 

17 KI0 

2 

1 JO16 

KI1 

17,21 KO0 

18 

2 

1 JO15 

KI2 

17,21 KO1 

19 

2 

1 JO14 

20 KI3 

2 

1 JO13 

21 KI4 

2 

1 JO12 

22 KI5 

2 

1 JO11 

23 KI6 

2 

1 JO10 

24 KI7 

2 

1 JO9 

25 

1 2 

26 

R213 

0/NA 

GND 

FPC/FFC/1MM/26P 

0603D_DFS 

ACES 

GND 

85202-26-02 

JO8 

SD[0..7] 

KBD_US/JP# 9 19,21 SD[0..7] 

+5V 

GND 

C1 

0.1U 

R4 

470K 

19,21 IRQ1 

0603 

50V 

0603 

19,21 IRQ12 

23 LEARNING 

GND 

G 

1 2 FAN# 

R3 

J502 

Q1 

33 

22 AUDIO_DJ_ON# 

1 

NDS356P 

0603 

17 KI0 

2 

+5V 

17 KI1 

3 

D1 

17 KI2 

A K +5V 

MA/3P/ST 

R372 

HIROSE 

10K 

21 KI5 

DF13B-3P-1.25V 

RLZ5.6B 

0603 

21 KI6 

21 KI7 

R2 

GND 

10K 

FAN_SPEED 

0603 

R373 

Q34 

1 0/NA 2 2 

DTC144WK 

0603D_DFS 

KO0 

79 

KO1 

78 

KO2 

77 

KO3 

76 

KO4 

75 

KO5 

74 

KO6 

73 

KO7 

72 

KO8 

67 

KO9 

66 

KO10 

65 

KO11 

64 

KO12 

63 

KO13 

62 

KO14 

61 

KO15 

60 

SD0 

82 

SD1 

83 

SD2 

84 

SD3 

85 

SD4 

86 

SD5 

87 

SD6 

88 

SD7 

89 

H8_PWRON_SB 49 

H8_WAKE_UP# 50 

SCI#/FAN_SPD 51 

H8_SCI 52 

53 

54 

55 

FAN# 

56 

H8_PWRON 14 

H8_RCIN# 13 

12 

KI0 

26 

KI1 

27 

KI2 

28 

KI3 

29 

KI4 

32 

KI5 

33 

KI6 

34 

KI7 

35 

P10/A0 

P11/A1 

P12/A2 

P13/A3 

P14/A4 

P15/A5 

P16/A6 

P17/A7 

P20/A8 

P21/A9 

P22/A10 

P23/A11 

P24/A12 

P25/A13 

P26/A14 

P27/A15 

P30/HDB0/D0 

P31/HDB1/D1 

P32/HDB2/D2 

P33/HDB3/D3 

P34/HDB4/D4 

P35/HDB5/D5 

P36/HDB6/D6 

P37/HDB7/D7 

P40/TMCI0 

P41/TMO0 

P42/TMRI0 

P43/TMCI1/HIRQ1 

P44/TMO1/HIRQ1 

P45/TMRI1/HIRQ1 

P46/PW0 

P47/PW1 

P50/TXD0 

P51/RXD0 

P52/SCK0 

P60/KEYIN0/FTCI 

P61/KEYIN1/FTOA 

P62/KEYIN2/FTIA 

P63/KEYIN3/FTIB 

P64/KEYIN4/FTIC 

P65/KEYIN5/FTID 

P66/KEYIN6/IRQ6 

P67/KEYIN7/IRQ7 

H8/F3437 

P70/AN0 

P71/AN1 

P72/AN2 

P73/AN3 

P74/AN4 

P75/AN5 

P76/AN6/DA0 

P77/AN7/DA1 

P80/HA0 

P81/GA20 

P82/CS1 

P83/IOR 

P84/IRQ2/TXD1/I 

P85/IRQ4/RXD1/C 

P86/IRQ5/SCK1/S 

P90/IRQ2/ESC2 

P91/IRQ1/EIOW 

P92/IRQ0 

P93/RD 

P94/WR 

P95/AS 

P96/0 

P97/WAIT/SDA 

MD0 

MD1 

PB0/XDB0 

PB1/XDB1 

PB2/XDB2 

PB3/XDB3 

PB4/XDB4 

PB5/XDB5 

PB6/XDB6 

PB7/XDB7 

PA0/KEYIN8 

PA1/KEYIN9 

PA2/KEYIN10 

PA3/KEYIN11 

PA4/KEYIN12 

PA5/KEYIN13 

PA6/KEYIN14 

PA7/KEYIN15 

/STBY/FVPP 

/NMI 

/RES 

XTAL 

EXTAL 

/RESO 

PQFP100_0.5MM 

38 

39 

40 

41 

42 

43 

44 I_CTRL 

45 BLADJ 

93 SA2 

94 H8_A20GATE 

95 H8_KBCS# 

96 IOR# 

97 IOW# 

98 H8_MCCS# 

99 BAT_CLK 

25 H8_SUSC# 

24 LID# 

23 POWERBTN# 

22 H8_THRM# 

19 SW_VDD5 

18 H8_SMI# 

17 H8_A20GATE 

16 BAT_DATA 

6 H8_MODE0 

5 H8_MODE1 

91 LED_CLK 

90 LED_DATA 

81 1 2 

80 R608 0/NA 0603D_DFS 

69 

68 KM_DATA 

58 M_DATA 

57 T_DATA 

48 EC_RI# 

47 BATT_DEAD# 

31 H8_PME# 

30 ADEN# 

21 H8_BAT_CLK 

20 KM_CLK 

11 M_CLK 

10 T_CLK 

8 H8_STBY# 

7 H8_SUSB 

1 H8_RESET# 

2 

3 

100 

R615 

1 2 

1M 0603 

I_LIMIT 23 

1 2 

+2.5V_DDR 

R364 22 

1 2 

R371 22 +VCC_CORE 

VDD5 

I_CTRL 24 

BLADJ 5,21 

SA2 19,21 

R233 

10K 

IOR# 19,21 

0603 

IOW# 19,21 

PWRSW# 

H8_SUSB 

LID# 21,22 

1 2 PWRSW# 

PWRSW# 22 

C606 

R232 

SW_VDD5 22 

0.1U 

1K 

50V 

0603 

0603 

GND 

LED_CLK 21 

LED_DATA 21 

H8_PWRON_RSM5V 22 

1 2 

H8_SIDE_IN# 11 

R687 470 

CHARGING 24 

1 2 

VDD5 

R688 47K 

T_DATA 21 

EC_RI# 16 

H8_WAKE_UP# 

ADEN# 22,23 

1 2 

VDD5 

1R706 10K/NA 2 BAT_CLK 

R1 2 BATT_DEAD 

BATT_DEAD 24 

R93 0/NA 0603D_DFS 

Q10 

T_CLK 21 

DTC144TKA 

GND 

VDD5 

H8_SMI# 

VDD5 

VDD5 

R241 

4.7K 

R611 

0603 

10K 

0603 

LID# 

Q18 

DTC144TKA 

R1 2 SUSB# 

SUSB# 3,4,9,18,21,22,26,28,29 

GND 

VDD3 

Pull high at ICH4 

Resume well power plane 

1 3 

WAKE_UP# 9,10 

Q21 

DTC144TKA 

VDD3 


Resume well power plane 

1 3 

EXTSMI# 9,10 

C 

X502 

Q33 

D8 

A K 

RLS4148/NA 

GND 

1 2 

16MHZ 

C610 TXC8X4.5 

68P 

C613 

68P 

R614 

100K 

0603 

H8_STBY# 

VDD5 

DTC144TKA 

VDD3 

B 

0603 

5% 

0603 

5% 

C609 

1U 

R359 


B 

VDD5 

VDD5 

GND GND 

0603 

10K 

0603 

RP41 

9,10 SCI# 

A 

D30 

K 

ADEN# 

H8_MODE0 

H8_MODE1 

1 

2 

3 

4 

10 

9 

8 

7 

EC_RI# 

BATT_DEAD# 

POWERBTN# 

+5V 

GND 

H8_PME# 

3 1 

Q32 

DTC144TKA 

PCI_PME# 9,10,15,16,17,18 

RLS4148 

R1 2 

H8_SCI 

5 6 H8_PME# 

SCI#/FAN_SPD 

Q17 

DTC144TKA 

2 R1 Q35 

DTC144TKA 

KI1 

KI0 

KI2 

KI3 

47K*8 1206 

RP502 

1 

10 

2 

9 

3 

8 

4 

7 

5 6 

KI4 

KI5 

KI6 

KI7 

RP39 

R374 

0/NA 

0603D_DFS 

+3V 

U12 

MAX809 

SOT23N 

3 

VCC 

RESET# 

2 

PWROK 5,9 

FAN_SPEED 

VDD5 VDD5 

R605 R603 

BAT_CLK 

BAT_DATA 

H8_SMI# 

47K*8 

R54 1 

R613 1 

R234 1 

1206 

2 4.7K 

0603 

2 4.7K 

0603 

2 4.7K 

0603 

T_CLK 

M_CLK 

KM_CLK 

1 

2 

3 

4 

5 

4.7K*8 

10 

9 

8 

7 

6 

1206 

T_DATA 

M_DATA 

KM_DATA 

VDD5 

809S 

R74 

100K 

0603 

VDD3 

R607 

10K 

10K 10K 

0603 

A 

3 H8_THRM_DATA 

3 

3 H8_THRM_CLK 

4 

9 A20GATE 

7 

1 R602 2 0603D_DFS 

19,21 ROMCS# 

8 

0/NA 

9 SB_THRM# 

11 

1 R604 2 0603D_DFS 

19 MCCS# 

14 

0/NA 

9 HRCIN# 

17 

18 

21 

22 

R601 

1 

22 SW_VDD5# 

1 2 

13 

0/NA 

0603 

R600 

U503 

1A1 1B1 

1A2 1B2 

1A3 1B3 

1A4 1B4 

1A5 1B5 

2A1 2B1 

2A2 2B2 

2A3 2B3 

2A4 2B4 

2A5 2B5 

1OE# VCC 

2OE# GND 

SN74CBTD3384 

QSOP24A 

2 

5 

6 

9 

10 

15 

16 

19 

20 

23 

24 

12 

THRM_DATA 

THRM_CLK 

H8_A20GATE 

H8_KBCS# 

H8_THRM# 

H8_MCCS# 

H8_RCIN# 

JS502 

1 2 

SHORT-SMT3 

1 

0603 0603 

+5V VDD5 

JO515 

2 

VDD5 

VDD3 

R610 

10K 

0603 

H8_SUSC# 

3 1 

Q508 

VDD5 

SUSC# 9,27 

U22 

MAX809 

SOT23N 

3 

VCC 

2 

RESET# 

809M 

GND 

R77 

100K 

0603 

GND 

D25 

2 

1 

BAW56 

B 1 

1K 

Q11 

R7 

10K 

0603 

3 

H8_RESET# 

C86 

0.01U 

0603 

GND 

2 R58 PWROK 

0603 

GND 

H8_RESET# 21 

GND 

H8_PWRON_SB 2 

Q5 

DTC144WK 

GND 

ICH_PWRBTN# 9 

A 

0/NA 

0603D_DFS 

C600 

0.1U 

0603 

50V 

OPEN-SMT3 

DTC144TKA 

MMBT3904L 

1 2 R57 

0 

0603D 

TEMP_ALERT# 3 

Title 


GND 

Size 

C 

Document 

Number 

411675300001 

Rev 

03 

1 

2 

D S 

1 

2 

1 3 

1 3 

1 

32 

1 

1 

2 

1 

2 

9 

59 

37 

4 

VCC1 

VCC2 

AVCC 

VCCB 

1 

2 

70 

71 

92 

15 

46 

36 

VSS1 

VSS2 

VSS3 

VSS4 

AVSS 

AVREF 


1 2 

3 

1 

2 

1 

2 

1 

1 2 

2 

1 

1 

2 

GND 

1 

2 

1 

2 

1 

1 

2 

3 

2 

1 

2 

E C 

1 3 

1 

2 

2 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

GND 

1 

GND 

1 

2 

2 

R1 

1 

2 

1 3 

1 

2 

2 

2 

2 

R1 

1 

2 

R1 

R1 

1 


1 


1 

2 

1 

2 

1 

2 

3 

1 

1 

2

5 

5 

4 

4 

3 

+5V 

D 

1 

3 

SW8 

2 

4 

KI6 

KI6 20 

JO53JO54 

1 

3 

SW7 

2 

4 

KI7 

KI7 20 

D 

JO56JO60 

5 

5 

1 2 

1 2 

17,20 KO0 

1 2 

GND 

GNDGND 

SW_LEFT 

KO0 

SCRL UP 

SCRL_DN 

20 T_DATA 

GND 

1 2 

1 

3 

TOUCH_PAD 

1 

3 

JO51 

GND 

SW4 

SW3 

TC010-PSS11CET 



2 

4 

5 

1 2 

2 

4 

5 

Flash ROM 

1 2 

JO55 

KI5 

SCRL_LEFT 

SCRL_RIGHT 

F3 

0.5A/POLYSW 


GND 

JO57 

miniSMDC050 

JO62 

JO52 

GND 

GND 

1 2 

L23 120Z/100M 1608 

1 2 

L22 120Z/100M 1608 

GND 

+3V 

8 

7 

6 

5 

1 

2 

3 

4 

GND 

1 2 

1 2 

R228 0 0603D 

1 2 

R227 0/NA 0603D_DFS 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

J2 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

1 

2 

GND 

1 

2 

C244 

0.1U 

0603 

50V 

1 2 

1 2 

GNDGND 

R1 

BATT_POWER# 

1 

3 

74VHC164 

KO1 

BATT_LED# 

1 

2 

1 2 

1 3 

Q29 

DTC144TKA 

3 

1 

3 

SW6 


2 

4 

5 

1 2 

GND GND 

R1 

2 

KI5 

2 

D 

D 

S 

S 

+3V_P 

14 

7 

GND 

2 

Q30 

2N7002 

G 

2 

U20A 

74AHC14_V 

TSSOP14 

1 

8 

+3V_P 

14 

7 

4 

+3V_P 

14 

7 

GND 

U20D 

U20B 

74AHC14_V 

TSSOP14 

9 

74AHC14_V 

TSSOP14 

3 

10 

+3V_P 

GND 

+3V_P 

14 

7 

C3 

0.1U/NA 

50V 

0603 

1 

2 

1 

2 

1 

2 

1 

2 

U20E 

74AHC14_V 

TSSOP14 

11 

Title 

Size 

C 

1 

2 

2 

2 

1 

2 

R1 

R1 

C4 

0.1U 

0603 

50V 

Document 

Number 

+3V_P 

GND 

1 

74AHC14_V R338 

TSSOP14 

13 1 2 

C332 

4.7U 

SW5 

CP1 

47PX4 

1206 

FPC/FFC-12P/0.5MM 

R341 

GND 

0805 

+80-20% GND 

GND 

1 

2 

GND 

6239-012-001-800 

1 2 

C JO59 

SW_RIGHT 

3 

4 

5 

CONN_ELCO6239_12 

291000151201 

180K 

C 


0603 

ENABLE_BKLT L3 1 2 120Z/100M 0603D 

1 

+5V 

L1 1 2 120Z/100M 0805C 

2 

3 

J504 

MA/11P/ST 

B 

19,20 SD[0..7] 

SD[0..7] 

19 SA18 

SD0 

SD1 

SD2 

SD3 

SD4 

SD5 

SD6 

SD7 

+5V 

C333 

0.1U 

0603 

50V 

GND 

13 

14 

15 

17 

18 

19 

20 

21 

1 

32 

16 

GND 

U19 

O0 A0 

O1 A1 

O2 A2 

O3 A3 

O4 A4 

O5 A5 

O6 A6 

O7 A7 

A8 

A9 

VPP A10 

A11 

A12 

A13 

A14 

A15 

VCC A16 

A17 

CE# 

OE# 

VSS WE# 

28F02-PLCC 

12 

11 

10 

9 

8 

7 

6 

5 

27 

26 

23 

25 

4 

28 

29 

3 

2 

30 

22 

24 

31 

SA0 

SA1 

SA2 

SA3 

SA4 

SA5 

SA6 

SA7 

SA8 

SA9 

SA10 

SA11 

SA12 

SA13 

SA14 

SA15 

SA16 

SA17 

ROMCS# 

MEMR# 

MEMW# 

SA[0..17] 

ROMCS# 19,20 

MEMR# 19 

MEMW# 19 

+5V +3V 

2 

SA[0..17] 19,20 

R48 

10K 

0603 

ENABLE_BKLT 

LED_DATA 

20 LED_DATA 

1 

2 

LED_CLK 

20 LED_CLK 

8 

H8_RESET# 

20 H8_RESET# 

9 

U513 

A 

B 

CLK 

CLR 

PCIRST#1 9,14 

Q9 

DTC144TKA 

Q8 

1 ENBL 

ENBL 5 

3 

2 

LID# 20,22 

BAW56 

VDD5 

3 

SCROLL# 

QA 

4 

NUM# 

QB 

5 

CAP# 

QC 

6 

QD 

10 AC_POWER# 

QE 

11 BATT_POWER# 

QF 

12 BATT_R# 

QG 

13 BATT_G# 

QH 

5,20 BLADJ 

BLADJ L2 1 2 

0603D 

120Z/100M 

FA1 

AC_POWER# 1 

8 

BATT_LED# 

2 

7 

BATT_G# 

3 

6 

BATT_R# 

4 5 

120OHM/100MHZ 

C6 

0.1U 

1 2 

0603 

VDD5S 

L4 

50V 

120Z/100M 

0805C 

GND 

+3V 

R336 

10K Q28 

0603 DTC144TKA 

18 SD_LED# 

1 3 

+3V 

4 

5 

6 

7 

8 

9 

10 

11 

K 

291000011101 

+5V 

A 1 2 

R354 330 

B 

7 

GND VCC 

14 

D24 

CL-190G 

74VHC164 

TSSOP14 

C663 

0.1U 

0603 

50V 

11 CD_LED# 

K 

A 1 2 

+5V_CDROM 

R306 

10K Q25 

RP47 

D18 

R352 330 

0603 DTC144TKA 

SA8 

SA9 

SA11 

SA10 

1 

2 

3 

4 

5 

10 

9 

8 

7 

6 

SA14 +3V 

SA13 

SA17 

GND 

GND 

11 HDD_LED# 

CL-190G 

K 

A 

D19 

1 2 

R349 330 

+5V 

18 SM_LED# 

1 3 

+3V 

4.7K*8 1206 

CL-190G 

SA18 

SA16 

1 

2 

3 

4 

RP45 

10 

9 

8 

7 

SA15 +3V 

SA12 

SD2 

SD1 

SD0 

SD3 

1 

2 

3 

4 

5 

RP506 

10 

9 

8 

7 

6 

SD5 

SD6 

SD7 

SD4 

+3V 

NUM# 

CAP# 

K 

A 

D23 

CL-190G 

K 

A 

1 2 

R353 330 

1 2 

18 MS_LED# 

R326 

10K 

0603 

1 

Q27 

DTC144TKA 

3 

5 6 

D20 

R350 330 

4.7K*8 1206 

CL-190G 

4.7K*8 1206 

SCROLL# K 

A 1 2 

A A 

D21 

R351 330 

RP503 

CL-190G 

SA4 

SA5 

SA6 

SA7 

1 

2 

3 

4 

5 

RP505 

10 

9 

8 

7 

6 

SA3 

SA2 

SA1 

SA0 

+3V 

19,20 IRQ1 

19,20 IRQ12 

19,20 IOR# 

19,20 IOW# 

1 

2 

3 

4 

5 

10 

9 

8 

7 

6 

MEMW# +3V 

MEMR# 

LED INDICATOR- From left to right 

4.7K*8 1206 

4.7K*8 1206 

CDROM HDD NUM CAP SCROLLMINIPCI CARD READER 

19 SA19 

20 T_CLK 

1 

2 

1 2 R644 

4.7K 0603 

1 

2 

L20 

120Z/100M 

2012 


KI5 20 

17,20 KO1 

SUSB# 3,4,9,18,20,22,26,28,29 

1 

2 

6 

14 

7 

U20C 

74AHC14_V 

TSSOP14 

5 

2 

R1 

12 

14 

7 

U20F 


1M 

0603 

Rev 

411675300001 03 


1 

Sheet 21 of 29

PWR_VDDIN 

OPEN-SMT4 

5 

F502 

5 

1 

2 

1 

2 

1 2 

FUSE_1206 

3216FF-1 

1A-1206 

GND GND 

U506 

1 

INPUT 

GND 

2 

3 

OUTPUT 

AMS3107 

SOT223 

H8_AVREF 

1 

2 

GND 

4 

4 

1 

2 

VDD5 

1 

2 

C616 

4.7U 

1206 

16V 

GND 

GND 

1A 

1A 

3 

1 

1 

2 

+5V_P 

1 

2 

3 

+5V_P 

For Lan 

U25 

+3V 

+5V 

D 

+3V_P 

+5V_P 

+3V_ON 

C267 

1U 

0603 

GND 

For USB 

+5V_ON 

C345 

1U 

0603 

4 

SOURCE3 

3 

SOURCE2 

2 

SOURCE1 

1 

VIN 

SI4788CY 

SO8 

U27 

4 

SOURCE3 

3 

SOURCE2 

2 

SOURCE1 

1 

VIN 

SI4788CY 

SO8 

DRAIN3 

DRAIN1 

DRAIN2 

GND 

DRAIN3 

DRAIN1 

DRAIN2 

GND 

5 

6 

7 

8 

5 

6 

7 

8 

C342 C343 

10U 1U 

1206 0603 

10V 

GND GND 

+5V 

C2 C344 

10U 1U 

1206 0603 

10V 

+1.25V_DDR_F 

C285 

1U 

0603 

GND 

SUSB# 1 2 

0603 R248 100 

JO50 

1 2 

OPEN-SMT4 

U14 

4 


3 


2 


1 

VIN 

GND 

SI4788CY 

SO8 

5 

6 

7 

8 

+1.25V_DDR 

C280 

C283 

10U 

1U 

1206 

0603 

10V 

GND 

GND 

20 PWRSW# 

20,21 LID# 

19 IRRX 

19 IRTX 

10 SIDE_IN# 

19 IRSEL0 

19 IRSEL1 

10,12 ACBITCLK 

10,12 ACSYNC 

10 ACSDIN1 

10,12 ACSDOUT 

10,12 ACRST# 

12 MODEM_SPK 

12 MONO_OUT 

R3771 0/NA 2 

0603 

J506 

1 

1 

3 

3 

5 

5 

7 

7 

9 

9 

11 

11 

13 

13 

15 

15 

17 

17 

19 

19 

21 

21 

23 

23 

25 

25 

27 

27 

29 

29 

31 

31 

33 

33 

35 

35 

37 

37 

39 

39 

41 

41 

43 

43 

45 

45 

47 

47 

49 

49 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

46 

48 

50 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

46 

48 

50 

1 

R12 

1 

R13 

2 

0/NA 

2 

0/NA 

USBOC1# 10 

USBP2+ 10 

USBP2- 10 

TPA+ 15 

TPA- 15 

TPB+ 15 

TPB- 15 

+3V 

ROUT+ 13 

ROUT- 13 

VDD3 

D 

A K 

D504 

RLZ5.6B 

1 

2 

1 

2 

1 

2 

PC569 

10U 

1206 

10V 

D S 

D 

S 

G 

G 

1 

2 

Q512 

SI2301DS 

Finger Printer connector 

+VCCP 

+1.05V_P 

+2.5V_DDR 

JO41 

1 

+2.5V_DDR_P 

2 

JO514 

1 2 

OPEN-SMT4 

JP_SMT4_DFS 

1.05V 

VDD3 

VDD1.5 

VDD5 

PQ1 

VDD5S 

VDD5 

Q37 

S D 

RSM5V 

R163 

1 2 

VDD5S 

OPEN-SMT4 

JP_SMT4_DFS 

JO39 

1 2 

OPEN-SMT4 

JP_SMT4_DFS 

JO513 

1 2 

OPEN-SMT4 

JP_SMT4_DFS 

C142 

0.1U 

0603 

50V 

U6 

3 

VIN 

VOUT 

1 

GND/ADJ 

AME1117 

SOT223 

2 

C139 

2.2U 

0805 

+80-20% 

S D 

PR20 SI2301DS/NA 

100K/NA 

0603 

PD3 

A K ADEN# 

ADEN# 20,23 

R378 

100K 

0603 

SI2301DS 

D27 

A K 

BAS32L 

0/NA 

0805C_DFS 

ADEN# 20,23 

VDD5 

R379 

47K 

0603 

A 

+1.25V_DDR_F 

+1.25V_DDR_P 

GND 

1 2 R182 

10K 0603 

0.1% 

GND 

BAS32L/NA 

+2.5V_DDR 

PQ2 

R1 2 

Q38 

R1 2 

H8_PWRON_RSM5V 20 

A 

JO516 

1 2 

R178 

DTC144TKA 

OPEN-SMT4 

JP_SMT4_DFS 

2K 

0603 286301117021 積甲 

DTC144TKA/NA 

GND 

GND 

1 

2 

1 2 

1 

2 

R622 

100K 

0603 

C 

GND 

GND 

GND 

GND 

SW_VDD5# 20 

MINISMDC110 

R616 

33K 

0603 

C111 

10U 

1206 

10V 

120Z/100M 

2012 

C612 

1000P 

0603 

R345 

100K 

0603 

C 

20 SW_VDD5 

SW_VDD5 1 2 R624 

0/NA 

0603D_DFS 

2 

Q510 

DTC144WK 

10 USBOC3# 

AUDIO_DJ_ON# 20 

9,11 PCIRST#0 

1 

0603 

2 R623 

0/NA 

R617 

47K 

0603 

GND 

USB1_GND 

JO65 

R344 

1K 

0603 

GND 

GND 

SW501 

4 

5 

GND 6 

7 

GND 

4V/0.3A 

SS-350-A12W-C 

297040100013 

GND 

+5V 

+5V_P 

JO48 

+1.8V 

+1.8V_P 

J3 

1 2 

OPEN-SMT4 

JO511 

1 2 

RSM5V 

U5 

VDD3 

1 

2 

3 

L525 

PLP3216S 

USBP3- 10 

USBP3+ 10 

JP_SMT4 

JO49 

OPEN-SMT4 

JP_SMT4_DFS 

3 

VIN 

4 

5 

+VCC_USB3 

B 

+3V 

1 2 

OPEN-SMT4 

JP_SMT4 

+3V_P 

+1.2V 

JO7 

1 2 

OPEN-SMT4 

JP_SMT4_DFS 

+1.2V_P 

C140 

0.1U 

0603 

50V 

GND 

VOUT 

1 

GND/ADJ 

AME1117 

SOT223 

1 2 R180 

2 

C141 

2.2U 

0805 

+80-20% 

HDR/MA-5 

ACES 

87152-0507 

L30 

1 2 

120Z/100M 

1608 

JO44 JO47 

+3V_P +5V_P 

R110 

10K 

0603 

B 

JO45 

+1.5V 

+1.5V_P 

0603 

750 

1 2 

OPEN-SMT4 

JO46 

1 2 

JO512 

1 2 

OPEN-SMT4 

JP_SMT4_DFS 

R181 

1.27K 

0603 

1% 

1% 

GND 

286301117021 積甲 

USB1_GND GND 

USB1_GND USB1_GND 

3,4,9,18,20,21,26,28,29 SUSB# 

1 3 

Q36 

DTC144TKA 

+3V_ON 

+5V_ON 


1 

2 

S 

G 

D 

S G 

D 

Q511 

SI2301DS 

1 

2 

3 

1 

2 

1 

2 

+5V 

G 

1 3 

D 

S G 

1 

2 

F501 

1 2 

1 

1 2 

2 

1 2 

1 2 

1 

2 

L526 

1 

4 

2 

1 2 

1 

2 

2 

2 

3 

1 

2 

G 

1 3 

+VCC_USB3 

D 

S G 

FM/25PX2/0.8MM 

SPEED 

K07X-X008-050 

291000015031 

1 2 

Title 

Size 

C 

1 2 

R18 

0/NA 

0603D_DFS 

1 

2 

VDD5 

1 

2 

Document 

Number 

1 2 

1 

2 

32 

R1 

1 

2 

R8 

0/NA 

0603D_DFS 

1 

2 

GND 

1 


Rev 

411675300001 03 


1 

Sheet 22 of 29

5 

5 

4 

4 

3 

D D 

BAV70LT1 

BAV70LT1 

PJ501 

JACK-3P/D2.0/H7 

IDJ-D22-6T 

1 

2 

3 

JO1 

SPARKGAP_6 

PF2 6.5A/32VDC 

A1 1 2 A2 

1 2 

1 2 

JO2 

SPARKGAP_6 

1 

2 

GND 

PC11 

1U 

0805 

10V 

PL2 

120Z/100M 

2012 

2 

1 

2 

A3 1 2 

A4 

B2 

B3 

B 

J501 

7 

6 

5 

4 

GNDB 

PR504 

4.99K 

0603 

1% 

GND 

PC3 

0.1U 

0603 

50V 

PR8 

100K 

0603 

1% 

PC8 

0.1U 

0603 

50V 

BAT_V 20 

B 

3 

2 

1 

B1 

BAT_T 20 

R/A-7P/2.5MM 

SUYIN 

250005MR07G100ZU 

PR503 

20K 

0603 

1% 

PC502 

0.1U 

0603 

50V 

GND 

VDD5 

JO501 

JP501 

A SPARKGAP_6 

SPARKGAP_6 

A 

GND GND 

GND 

1 

1 2 

GND 

PF1 6.5A/32VDC 

1 2 

VDD5 

1 

2 

GND 

1 

2 

PC5 

0.1U 

0603 

50V 

PR502 

GND 0 

0603 

1 2 

PR501 

1 2 

0 

0603 

PD502 

PD501 BAV99 

2 

3 

1 

BAV99 

3 

2 

JO3 

OPEN-SMT4 

2 

PL1 

120Z/100M 

2012 

2 

1 

1 

1 

1 

2 

1 

2 

VDD5 

3 

2 

1 

PR30 

470K 

0603 

PQ5 

SI4835DY 

SO8 

S 

PR1 

301K 

0603 

1% 

4 

1 

2 

1 

2 

G 

D 

PR39 

100K 

0603 

8 

7 

6 

5 

D PQ7 

PR508 

GND 

20 LEARNING 

LEARNING G S 2N7002 PJO3 

OPEN-SMT4 

33K 

0603 

C PR41 

ADEN# 20,22 

C 

PU3 

1M 

4 

5 

6 

RS+ 

RS- 

OUT 

VCC 

GND1 

GND0 

3 

2 

1 

PC18 

0.1U 

0603 

G 

D PQ505 

S 2N7002 

SOT23_FET 

BATT 24 

MAX4173FEUT-T 

0603 

PR18 

SOT26 

50V 

10 

GND 

0603 

2 

PQ503 

GND 

PC4 

PC501 

DTC144WK 

0.01U 

1000P 

SOT23AN_1 

50V 

0603 

10% 

25V 

GND 

0603D 

10% 

1 

2 

1 

2 

PL3 

120Z/100M 

PC9 2012 

0.1U 

0603 

50V 

I_LIMIT 20 

1 2 

1 

2 

PC16 

1U 

0805 

25V 

1 

2 

A K 

1 

2 

PD2 

RLZ24D 

MLL34B 

PL8 

120Z/100M 

2012 


1 

2 

PC23 

0.1U 

0603 

50V 

1 

2 

2 

PR24 

.02 

2512 

1% 

1 

1 

2 

BAT_C 20 

BAT_D 20 

1 

2 

1 

2 

D 

S 

1 2 

BATT 24 

3 

ADINP 24 

1 

2 

PR506 

324K 

0603 

3 

1 

GND 

PD4 

1 

3 

2 

1 

2 

PR37 

4.7K 

0805 

1 

2 

GND 

PR29 

4.7K 

0805 

PWR_VDDIN 

PD5 

1 

3 

2 

1 

2 

D 

S 

SBM1040 

2 

PD7 

2 

3 

1 

PR507 

1 2 

100K 

0603 

2 

4 

G 

5 1 

2 

3 

S 

D 

6 

7 

8 

1 

2 

GND 

PQ501 

SI4835DY 

SO8 

4 

G 

5 1 

2 

3 

S 

D 

6 

7 

8 

1 

2 

PQ502 

SI4835DY 

SO8 

Title 

Size 

C 

1 

2 

GND 

Document 

Number 

PC30 

1000P 

0603 

DVMAIN 

1 

2 

1 

PC507 

0.1U 

0603 

50V 


Rev 

411675300001 03 


1 

Sheet 23 of 29

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

CHARGING 

=11.0875V 

411675300001 03 


C 

24 29 


Title 

Size 

Document 

Number 

Rev 


2IN+ 

1.25V 

LI_OVP 

L5 

LI_OVP 

L2 

L1 

CHARGING 

CHARGING 

REF 

2IN+ 

1.25V 

L4 

L6 

L3 

GND 

VDD5 

GND 

GND 

GND 

GND GNDB 

GND 

GND 

GND 

GND 

GND 

VDD5 

GND 

DVMAIN 

GND 

PL501 

BEAD_120Z/100M 

0805D 

1 2 

PR27 

680K 

0603 

1% 

1 

2 

PR509 

4.7K 

0603 

1 

2 

PR21 

10K 

0603D 

1% 

1 

2 

PQ508 

DTA144WK 

SOT23AN_1 

1 

2 

3 

+ 

- 

PU4B 

LMV393M 

SSOP8 

5 

6 

7 

8 

4 

PD504 

B340LA 

DC2010 

A K 

D 

S 

PQ3 

2N7002 

SOT23_FET 

G 

D 

S 

PC10 

0.1U 

50V 

0603 

1 

2 

PR5 

130K 

0603 

0.1% 

1 

2 

+ PC508 

15U 

25V 

7243 

1 

2 

PC2 

0.1U 

50V 

0603 

1 

2 

D 

S 

PQ507 

2N7002 

SOT23_FET 

G 

D 

S 

PL502 

33UH 

CDRH124 

1 2 

PQ506 

MMBT2222A 

B 

E C 

PC14 

0.1U 

50V 

0603 

1 

2 

+ PC505 

15U/NA 

25V 

7243 

1 

2 

PR26 

2.49K 

0603 

1% 

1 

2 

PF501 

FUSE_1206 

1A-1206 

1 2 

G 

D 

S 

PQ504 

SI4835DY 

SO8 

8 

7 

6 

4 

5 

1 

3 

2 

PC6 

0.1U 

25V 

0603 

20% 

1 

2 

PJO2 

OPEN-SMT4 

1 2 

PC20 

0.1U 

0603 

1 

2 

PR511 

100K 

0603D 

1 

2 

PR19 

33K 

0603 

1 2 

+ PC506 

15U/NA 

25V 

7243 

1 

2 

PD503 

B340LA 

DC2010 

A K 

PC17 

1000P 

0603 

10% 

1 

2 

PR25 

10K 

0603 

1% 

1 

2 

PR12 

15K 

0603 

1% 

1 

2 

PR16 

787K 

0603 

1% 

1 

2 

PC503 

0.01U 

50V 

0603 

10% 

1 

2 

PC26 

0.1U 

16V 

0603 

10% 

1 2 

PR28 

6.19K 

0603 

1% 

1 2 

PR10 

10K 

0603 

0.1% 

1 

2 

PR510 

4.7K 

0603 

1 

2 

PC13 

0.1U 

50V 

0603 

1 

2 

PQ4 

SCK431LCSK-.5 

SOT23N 

3 2 

1 

PR505 

.02 

2512 

1% 

1 2 

PR3 

294K 

0603 

1% 

1 

2 

PD505 

BAS32L 

MLL34B 

A 

K 

PJS501 

SHORT-SMT3 

1 

2 

PR22 

100K 

0603 

1 

2 

PD1 

RLZ20C 

MLL34B 

A K 

PR4 

4.7 

0603 

1 2 

PR11 

1M 

0603 

1 

2 

PU1A 

SI4925DY 

SO8 

1 

2 

7 

8 

PC15 

150P 

0603 

1 

2 

PC19 

0.1U 

50V 

0603 

1 2 

PR14 

100K 

0603D 

1 

2 

PJO1 

OPEN-SMT4 

1 2 

PU2 

TL594C 

SO16 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

1IN+ 

1IN- 

FEEDBACK 

DTC 

CT 

RT 

GND 

C1 

E1 

E2 

C2 

VCC 

OUTPUTCTRL 

REF 

2IN- 

2IN+ 

PR17 

3.3K 

0603 

1 

2 

PR6 

23.2K 

0603 

0.1% 

1 

2 

PR2 

976K/NA 

0603 

1% 

1 

2 

PR9 

47K 

0603 

1 

2 

PC24 0.01U 

50V 

0603 

10% 

1 2 

PU1B 

SI4925DY 

SO8 

3 

4 

6 

5 

PR15 

100K 

0603D 

1 2 

PC1 

10U_NA 

25V 

1210 

1 

2 

PR31 

249K 

0603 

1% 

1 

2 

PC21 

1U 

16V 

0805 

1 

2 

+ 

- 

PU4A 

LMV393M 

SSOP8 

3 

2 

1 

8 

4 

PC25 

0.01U_NA 

50V 

0603 

10% 

1 2 

PR13 

100K 

0603 

1 

2 

PC12 

0.1U 

50V 

0603 

1 

2 

PC504 

0.01U 

50V 

0603 

10% 

1 

2 

PR23 

63.4K_NA 

0603 

1% 

1 2 

PC570 

10U 

25V 

1210 

1 

2 

PC7 

0.01U 

50V 

10% 

0603D 

1 2 

+ PC509 

15U 

25V 

7243 

1 

2 

PR7 

10K 

0603 

0.1% 

1 

2 

ADINP 

23 

BATT_DEAD 20 

BATT 23 

I_CTRL 

20 

CHARGING 

20 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

411675300001 03 


C 

25 29 


Title 

Size 

Document 

Number 

Rev 


5V_2 

INTVCC 

BG1 

3V_1 

SENSE2+ 

INTVCC 

SENSE1+ 

SENSE1- 

DVMAIN_D 

BG2 

SENSE2- 

GND 

GND 

GND 

+3V_P 

SGND 

+5V_P 

GND 

GND 

GND 

GND 

GND 

DVMAIN 

GND 

GND 

+5V_P 

GND 

GND 

PC92 

10U 

16V 

1206 

1 

2 

PC107 

100P 

0603D 

10% 

1 

2 

PC105 

1000P 

0603D 

1 

2 

PC101 

0.1U 

50V 

0603D 

1 

2 

PL4 

120Z/100M 

2012 

1 2 

G 

D 

S 

PU19B 

AO4900 

SO8 

2 

8 

7 

1 

PR80 

63.4K 

0603 

1% 

1 2 

PC81 

0.1U 

50V 

0603D 

1 

2 

+ PC78 

150U 

7343 

6.3V 

1 

2 

PC90 

0.1U 

50V 

0603D 

1 

2 

PR94 

4.75K 

0603D 

1% 

1 

2 

PC58 

0.1U 

50V 

0603D 

1 

2 

PU23 

LTC3728L 

HVQFN32_1 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

32 

31 

30 

29 

28 

27 

26 

25 

24 

23 

22 

21 

20 

19 

33 

34 

35 

36 

37 

VOSENSE1 

PLLFLTR 

PLLIN 

FCB 

ITH1 

SGND 

3.3VOUT 

ITH2 VOSENSE2 

NC0 

SENSE2- 

SENSE2+ 

RUN/SS2 

TG2 

SW2 

NC1 

BOOST2 

BG2 

NC3 

SENSE1- 

SENSE1+ 

NC2 

RUN/SS1 

PGOOD 

TG1 

SW1 

BOOST1 

VIN 

BG1 

EXTVCC 

INTVCC 

PGND 

SGND1 

SGND2 

SGND3 

SGND4 

SGND5 

PC79 

0.1U 

50V 

0603D 

1 

2 

PR81 

20K 

1% 

0603D 

1 2 

PC109 

100P 

0603D 

10% 

1 

2 

PC84 

180P/NA 

0603D 

5% 

1 2 

PL512 

10UH 

CDRH127-100MC 

1 2 

PC104 

1000P 

25V 

10% 

0603D 

1 2 

PC102 

1000P 

25V 

10% 

0603D 

1 2 

PR100 

8.06K 

0603D 

1% 

1 

2 

PC85 

180P/NA 

0603D 

5% 

1 2 

PC62 

10U 

25V 

1210 

20% 

1 

2 

PR97 

10K/NA 

0603D 

1 2 PC106 

0.01U 

0603D 

1 2 

PL514 

10UH 

CDRH127-100MC 

1 2 

PC83 

180P/NA 

0603D 

5% 

1 2 

PC75 

10U/NA 

10V 

1210 

1 

2 

+ PC70 

150U 

7343 

6.3V 

1 

2 

+ 

PC63 

15U 

25V 

7243 

1 

2 

PC97 

1000P 

0603 

10% 

1 

2 

PD510 

B140 

DC2010 

A K 

PR99 

1.13K/NA 

0603D 

1 

2 

PC60 

0.1U 

50V 

0603D 

1 

2 

PC77 

10U/NA 

10V 

1210 

1 

2 

G 

D 

S 

PU18 

SI4800DY 

SO8 

8 

7 

6 

4 

5 

2 

3 

1 

PC91 

180P/NA 

0603D 

5% 

1 2 

PC108 

1500P 

50V 

0603D 

10% 

1 

2 

PC513 

1000P 

25V 

0603D 

10% 

1 

2 

PC95 

1000P 

0603 

10% 

1 

2 

+ PC59 

15U 

25V 

7243 

1 

2 

G 

D 

S 

PU503 

SI4832DY 

SO8 

8 

7 

6 

4 

5 

2 

3 

1 

D 

S 

PQ6 

2N7002 

SOT23_FET 

G 

D 

S 

PC87 

0.1U 

50V 

0603D 

1 

2 

PJS1 

SHORT-SMT1 

1 2 

PR70 

.01 

2512 

1% 

1 2 

PD9 

BAW56 

SOT23N 

2 

1 

3 

PR98 

0 

0603 

1 

2 

PR83 

107K 

0603 

1% 

1 2 

PR89 

0 

0603D 

1 2 

+ PC71 

150U 

7343 

6.3V 

1 

2 

PC61 

1000P 

25V 

0603D 

10% 

1 

2 

PC88 

0.1U 

50V 

0603D 

1 

2 

PR71 

0.008 

2512 

1% 

1 2 

+ PC76 

150U 

7343 

6.3V 

1 

2 

PR86 

20K 

1% 

0603D 

1 2 

D 

G 

S 

PU19A 

AO4900 

SO8 

4 

5 

6 

3 

D 

S 

PQ14 

2N7002 

SOT23_FET 

G 

D 

S 

+S3V_P_EN# 

27 


5 

5 

4 

4 

3 

D D 

1 

5 

8 

7 

3 

GND 

C 

+1.5V_P 

PC538 

0.1U 

0603 

50V 

PC540 

+ 150U 

7343 

2.5V 

20% 

PC541 

10U 

1210 

25V 

2 

3 

6 

7 

8 

PC43 

0.1U_NA 

6 

5 

2 

1 

PC539 

+ 150U 

7343 

2.5V 

20% 

+1.8V_P 

PC537 

0.1U_NA 

0603 

50V 

C 

SI4800DY 

0603 

GND 

PR57 SO8 

20K 

0603 

1% 

50V 

GND 

PC42 

0.1U_NA 

0603 

50V 

PR58 

26.1K 

0603 

1% 

GND 

1 

2 

1 

2 

3,4,9,18,20,21,22,28,29 SUSB# 

1 

2 

1 

2 

1 

2 

R1 

0/NA 

0603D_DFS 

PR56 

10K 

0603 

1% 

GND 

TP11 

TOUCHPAD_10 

S PU14 

4 

1 2 

G 

D 

GND 

1 

2 

3 

4 

5 

PU13 

DRV1 

ADJ1 

EN1 

PGD1 

GND 

IN 

DRV2 

ADJ2 

EN2 

PGD2 

10 

9 

8 

7 

6 

SC338 

PSOP10_0.5MM 

B B 

A A 


1 

1 

2 

3 

D 

2.5V_IN 

PU15 

SI4800DY 

SO8 

1 

2 

G 

GND 

4 

1 

2 

PC544 

0.1U 

0805 

20% 

S 

GND 

1 

2 

+5V_P 

PC543 

10U 

1210 

25V 

1 

2 

1 

2 

TP10 

TOUCHPAD_10 

1 

1 

2 

PR55 

10K 

0603 

1% 

GND 

PC542 

10U 

1210 

25V 

1 

2 

PC545 

0.1U 

0603 

50V 

1 

2 

1 

2 

2 

PL517 

1 2 

120Z/100M 

2012 

2 

+2.5V_DDR 

Title 

Size 

C 

Document 

Number 

1 


Rev 

411675300001 03 


1 

Sheet 26 of 29

5 

5 

4 

4 

3 

D D 

1 

2 

GND 

1 

2 

PC86 

1000P 

0603 

10% 

1 

2 

DVMAIN 

1 

2 

1 

2 

GND 

1 

2 

1 

2 

1 

2 

PR73 

20K 

0603 

1% 

PC72 

1000P/NA 

0603 

GND 

1 

2 

1 

2 

PR76 

10K 

0603 

1% 

PL5 

1 2 

120Z/100M 

2012 

AGND1 

A K 

8 

7 

6 

5 

3 

2 

1 

D PU21 

SI4800DY 

G SO8 

4 

S 

2.5DH1 

PR84 

750K 

0603 

1% 

GND AGND2 

1 

2 

1 

2 

+ PC563 

15U/NA 

7243 

25V 

PC103 

0.1U 

0603 

50V 

A 

K 

1 

2 

1 

2 

B 

GND 

+5V_P 

PR82 

0 

0603 

1.25DL1 

+ 

B 

PC567 

TP24 

TOUCHPAD_10 

PR95 

470K 

0603 

PC80 

0.1U 

0603 

50V 

PC82 

4.7U 

0805 

+80-20% 

PC99 

4.7U 

0805 

+80-20% 

G 

2 

S 

AO4900 

SO8 

PD12 

B140 

DC2010 

PC568 

0.01U 

50V 

10% 

0603D 

330U 

7343 

2.5V-TPE 

1 

PGOOD2 

GND 

1 2 PR102 

0603 

0/NA 

1 2 PR103 

0603 

0 

PC68 

0.01U 

50V 

10% 

0603D 

PD10 

BAS32L 

C +2.5V_DDR_P 

C 

2.5V_DDR_1 

AGND1 

PC66 

0.01U 

50V 

10% 

0603D 

+ PC564 

10U 

1210 

25V 

20% 

FBK1 

REFIN 

2.5DL1 

REFIN 

GND 

VDDP1-2 

FBK1 

+2.5V_DDR_P 

1.25DH1 

G 

4 

PU5A 

D 

PGOOD1 

PC67 

220U 

7343 

4V 

+ 

1 2 

PC93 

0.1U 

50V 

0603 

1 2 

PC565 

PL513 

1 2 

1 

4.7UH 

2 

PU22 

PR79 

0 

0603 

PR74 

470K 

0603 

220U 

7343 

4V 

PR72 

80.6K 

0603 

1% 

PC74 

1000P_NA 

0603 

10% 

PR75 

10K 

0603 

1% 

D128C 

20% 

PD511 

B140 

PC94 

1000P 

0603 

10%,X7R 

PU20 

IRF7822 

D SO8 

G 

4 

S 

PR78 

5.62K 

0603 

1 1% 

PC89 

1 2 

0.1U 

50V 

0603 

2 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

PGND1 

DL1 

VDDP1 

ILIM1 

LX1 

DH1 

BST1 

REFIN 

TON2 

REFOUT 

VCCA2 

FBK2 

PGOOD2 

AGND2 

AGND1 

PGOOD1 

FBK1 

VCCA1 

VOUT1 

TON1 

EN/PSV1 

BST2 

DH2 

LX2 

ILIM2 

VDDP2 

DL2 

PGND2 

28 

27 

26 

25 

24 

23 

22 

21 

20 

19 

18 

17 

16 

15 

1 

PR85 

1M 

0603 1% 

2 

PC566 

1000P 

0603 

25V 

10% 

1 

2 

1 

2 

8 

7 

6 

5 

3 

2 

1 

20 RSMPWRON 

9,20 SUSC# 

D PQ15 

A G S 2N7002 

SOT23_FET 

A 


1 

PC98 

0.1U/NA 

0603 

50V 

2 

3 

1 

2 

1 

2 

SC1486 

TSSOP28 

1 2 

PR91 

10 

0603 

1 

2 

GND 

VDD5 

1 

2 

DVMAIN_D1 

PC69 

1000P 

0603 + PC65 

25V 15U 

10% 7243 

25V 

PC100 

4.7U 

0805 

+80-20% 

1 2 

PR92 

0 

0603 PR77 

1 2 

1 

2 

10 

0603 

1 2 

1 

2 

D 

S 

PR101 

1M 

0603 

GND 

PR96 

100K 

0603 

1 

2 

G 

GND 

D 

S 

1 

2 

D PQ16 

S 2N7002 

SOT23_FET 

GND 

VDD5 

1 2 

A 

K 

PR93 

10K 

0603 

1% 

VDDP1-2 

PR90 

2 1 

10 

0603 

PD11 

BAS32L 

+S3V_P_EN# 25 

1 

2 

GND 

2 

PC96 

10U 

1206 

10V 

2 

1.25V_DDR_1 

5 

6 

3 

7 

8 

1 

S 

AO4900 

SO8 

PU5B 

D 

GND 

1 

2 

GND 

A K 

Title 

Size 

C 

Document 

Number 

+5V_P 

1 

2 

PL515 

1 2 

3.3UH 

CDRH124 

1 

TP20 

TOUCHPAD_10 

1 


+1.25V_DDR_P 

Rev 

411675300001 03 


1 


1 

2 

1 

2

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

411675300001 03 


C 

28 29 


Title 

Size 

Document 

Number 

Rev 


1.05V_1 

1.2V_2 

DVMAIN_D2 

SENSE1.05+ 

TBG2 

INTVCC1 

TBG1 

SENSE1.05- 

SENSE1.2+ 

INTVCC1 

SENSE1.2- 

TSW1 

GND 

GND 

GND 

+1.2V_P 

+5V_P 

GND 

GND 

GND 

VDD5 

SGND2 

GND 

GND 

GND 

GND 

+1.05V_P 

+3V_P 

DVMAIN 

GND 

PC558 

1000P 

0603 

10% 

1 

2 

PL510 

3.3UH 

CDRH124 

1 2 

PR60 

4.75K 

0603D 

1% 

1 

2 

PC561 

0.1U 

50V 

0603D 

1 

2 

PR528 

10K/NA 

0603D 

1 

2 

D 

S 

PQ8 

2N7002 

SOT23_FET 

G 

D 

S 

PC557 

1000P 

25V 

10% 

0603D 

1 2 

PR65 

0 

0603D 

1 2 

PC547 

180P/NA 

0603D 

5% 

1 2 

PR64 

20K 

1% 

0603D 

1 2 

PJS502 

SHORT-SMT1 

1 2 

D 

G 

S 

PU16A 

AO4900 

SO8 

4 

5 

6 

3 

+ PC548 

330U 

7343 

2.5V-TPE 

1 

2 

D 

G 

S 

PU17A 

AO4900 

SO8 

4 

5 

6 

3 

PR67 

1.13K/NA 

0603D 

1 

2 

PR527 

8.06K 

0603D 

1% 

1 

2 

PC554 

0.1U 

50V 

0603D 

1 

2 

PL509 

120Z/100M 

2012 

1 2 

PC553 

10U 

25V 

1210 

20% 

1 

2 

PC550 

1500P 

50V 

0603D 

10% 

1 

2 

PR525 

6.34K 

0603 

1% 

1 2 

PC44 

1000P 

25V 

0603D 

10% 

1 

2 

+ PC48 

15U 

25V 

7243 

1 

2 

PC47 

1000P 

25V 

0603D 

10% 

1 

2 

PD509 

BAW56 

SOT23N 

2 

1 

3 

G 

D 

S 

PU17B 

AO4900 

SO8 

2 

8 

7 

1 

PC51 

10U/NA 

10V 

1210 

1 

2 

PC546 

0.1U 

50V 

0603D 

1 

2 

PC52 

0.1U 

50V 

0603D 

1 

2 

PC49 

100P 

0603D 

10% 

1 

2 

PC556 

1000P 

25V 

10% 

0603D 

1 2 

PR59 

.01 

2512 

1% 

1 2 

+ PC45 

330U 

7343 

2.5V-TPE 

1 

2 

PC549 

180P/NA 

0603D 

5% 

1 2 

G 

D 

S 

PU16B 

AO4900 

SO8 

2 

8 

7 

1 

PC53 

0.1U 

50V 

0603D 

1 

2 

PC552 

0.01U 

0603D 

1 2 

PC55 

0.1U 

50V 

0603D 

1 

2 

PL508 

3.3UH 

D124C 

1 2 

PR69 

100K 

0603 

1 

2 

PR62 

.01 

2512 

1% 

1 2 

+ 

PC46 

15U 

25V 

7243 

1 

2 

PC551 

100P 

0603D 

10% 

1 

2 

D 

S 

PQ12 

2N7002 

SOT23_FET 

G 

D 

S 

PC560 

10U 

16V 

1206 

1 

2 

PC57 

180P/NA 

0603D 

5% 

1 2 

PC559 

1000P 

0603 

10% 

1 

2 

PC562 

0.1U 

50V 

0603D 

1 

2 

PR68 

1M 

0603 

1 

2 

PC54 

180P 

0603D 

5% 

1 2 

PR66 

0 

0603 

1 

2 

PR526 

20K 

1% 

0603D 

1 2 

PR61 

100K 

0603 

1 

2 

D 

S 

PQ11 

2N7002 

SOT23_FET 

G 

D 

S 

PC50 

1000P 

0603D 

1 

2 

+ PC33 

330U 

7343 

2.5V-TPE 

1 

2 

PC56 

0.1U 

50V 

0603D 

1 

2 

PR63 

10K 

0603 

1% 

1 2 

PU502 

LTC3728L 

HVQFN32_1 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

32 

31 

30 

29 

28 

27 

26 

25 

24 

23 

22 

21 

20 

19 

33 

34 

35 

36 

37 

VOSENSE1 

PLLFLTR 

PLLIN 

FCB 

ITH1 

SGND 

3.3VOUT 

ITH2 VOSENSE2 

NC0 

SENSE2- 

SENSE2+ 

RUN/SS2 

TG2 

SW2 

NC1 

BOOST2 

BG2 

NC3 

SENSE1- 

SENSE1+ 

NC2 

RUN/SS1 

PGOOD 

TG1 

SW1 

BOOST1 

VIN 

BG1 

EXTVCC 

INTVCC 

PGND 

SGND1 

SGND2 

SGND3 

SGND4 

SGND5 

VCCP_PWRGD 

29 

SUSB# 

3,4,9,18,20,21,22,26,29 


5 

5 

4 

4 

3 

D D 

VID[0..5] 

+5V_P 

VID0 

VID1 

VID2 

VID3 

VID4 

VID5 

SUSPEND MODE DAC =0.748V BOOT MODE DAC =1.212V 

1 

2 

RUNPWROK 

PR534 

301K 

0603 

1% REF_CORE 

1 2 

1 

2 

VDD5 

RUNPWROK 

GND_A 

REF_CORE 

+5V_P 

D PQ510 

PR105 

1.96K 

A 

G S 2N7002 

SOT23_FET 

0603 

1% 

CORE_CLKEN# 4 

VRMPWRGD 9 

A 

3,4,9,18,20,21,22,26,28 SUSB# 

PR518 

1 2 

G 

D 

S 

PQ509 

2N7002 

SOT23_FET 

VCCP_PWRGD 28 

DPRSLPVR 9,10 

STOP_CPU# 4,9 

0 

0603 

1 

2 

PR517 

1M 

0603 

GND 

PR40 

0 

0603 

1 2 

PR43 

0 

0603 

1 2 

1 

2 

DVMAIN 

GND 

1 2 

+3V 

PR104 

0 

0603 

5 

6 

7 

8 

GND_A 

D 

G 

PU507 

FDS6694 

SO8 

4 

1 2 

PR35 

C 

PR536 

10 

0603 

PR537 

S 

.001 

2512C 

1% 

C 

10K 

1 2 

GND_A 

+VCC_CORE 

OAIN- 

1 2 OAIN+ 

CSP+ 

PC576 

CSN- 

100P 

0603 

10% 

0603 

VRMPWRGD 

1 2 

PC529 

0.1U 

0805 

D 

G 

4 

PU504 

IRF7822 

SO8 

PL507 

1UH/NA 

15% IHLP-5050CE 

1 2 

PR33 

.001/NA 

2512C 

1% 

1 2 

+ 

+VCC_CORE 

GND_A 

X7R 

PC28 

PC579 

0.1U 

0805 

X7R 

PU505 

MAX1907 

HVQFN40_1 

PC577 

47P 

0603 

10% 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

GND 

CC 

POS 

NEG 

FB 

OAIN- 

OAIN+ 

CSP 

CSN 

DPSLP 

GND3 

GND2 

GND1 

TON 

TIME 

CLKEN 

IMVPOK 

SYSPOK 

SUS 

V+ 

DH 

LX 

BST 

GND5 

GND4 

43 

42 

41 

40 

39 

38 

37 

36 

35 

34 

33 

32 

31 

45 

44 

220U 

7243 

2.5V 

+ PC31 

PR32 

200 

0603 

+ 

220U 

7243 

2.5V 

PC515 

PR535 

49.9K 

0603 

D 

G 

PU508 

D 

FDS6694/NA 

SO8 

G 

PU509 

FDS6694 

SO8 

1% 

4 

4 

PC575 

1U 

0805 

S 

S 

PL506 

0.68UH 

HK-AE30A0R5 

10V 

1 2 

2 1 

1 2 

PR538 

PR539 

2.7K 

PR540 0603 

432 

100K 

0603 

0603 

1% 

1% 

PD508 

B140 

D 

G 

4 

PU506 

IRF7822 

SO8 

D 

G 

4 

PU501 

IRF7822 

SO8 

PR36 

200 

0603 

220U 

7243 

2.5V 

PC518 

0.1U 

0603 

50V 

DC2010 

1 

2 

1 

2 

PR49 

0 

0603 

1 2 

PR34 

0 

0603 

1 2 

PR42 

0_NA 

0603 

1 2 

1 

2 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

1 

2 

PR521 

100K 

0603 

VCC 

ILIM 

REF 

SHDN 

S2 

S1 

S0 

B2 

B1 

B0 

D5 

D4 

D3 

D2 

D1 

D0 

DD0 

PGND 

DL 

VDD 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

1 

2 

1 

2 

1 

2 

1 

2 

PR556 

1 2 

100K 

0603 

D 

S 

PR38 

0 

0603 

1 2 

1 

2 

1 

2 

2 

1 

A K 

1 

2 

1 

2 

PL7 

120Z/100M 

2012 

1 2 

1 2 

PL6 

120Z/100M 

2012 

PC27 

1000P 

0603 

1 

2 

3 

5 

6 

7 

8 

GND +5V_P 

PD506 

B340LA 

DC2010 

+ 

PR45 

0 

0603 

VID5 

B 

VID4 

B 

VID3 

VID2 

VID1 

VID0 

1 2 

PR50 

0 

0603 

GND 

CSP+ 

PC32 

S 

S 

1 2 

PR542 

0 

0603 

PR541 

28K 

PC527 

4700P 

0603 

220U 

7243 

2.5V 

+ PC517 

0.1U 

0603 

50V 

0603 

PC531 

PR44 

1% 

10U 

0 

1206 

0603 

10V 

PR47 

0 

0603 PR48 

0 

0603 

PR51 

0 

0603 

1 

JS6 

1 

2 PR54 

0 

1 

2 PR52 

0 

0603 

2 

SHORT-SMT1 

0603 

PC29 

PC578 

0.1U 

0603 

25V 

20% 

+ 220U 

7243 

2.5V 

PR46 

0 

0603 

1 

PR53 

0 

0603 

2 

PC521 

S 

PD507 

B340LA 

DC2010 

220U 

7243 

2.5V 

3 VID[0..5] 

1 

2 

PC574 

0.22U 

16V 

0603 

10% 

1 2 

1 2 


D 

S 

1 

2 

3 

1 2 

3 

5 

6 

7 

8 

1 

2 

3 

5 

6 

7 

8 

1 

2 

3 

5 

6 

7 

8 

1 

2 

3 

5 

6 

7 

8 

1 

2 

3 

A K 

1 

2 

DD_CPU 

+ PC524 

10U/NA* 

25V 

1 

2 

A K 

1 

PC519 

10U 

1210 

25V 

20% 

2 

OAIN+ 

OAIN- 

2 

PC512 

10U 

1210 

25V 

20% 

CSN- 

2 

1 

2 

1 

2 

GND 

PR554 

300 

0603 

1 2 

1 2 

PR555 

1K 

0603 

1% 

PC522 

10U 

1210 

25V 

20% 

1 

2 

PC510 

10U 

1210 

25V 

20% 

1 

2 

1 

2 

PC511 

10U 

1210 

25V 

20% 

1 

2 

1 

2 

1 

2 

PC523 

10U 

1210 

25V 

20% 

1 

2 

Title 

Size 

C 

1 

2 

1 

2 

PC22 

0.1U 

0603 

50V 

Document 

Number 

1 

2 

1 

2 

PC526 

1000P 

0603 

25V 

10% 

1 

2 

1 

2 

1 

PC525 

1000P 

0603 

25V 

10% 


Rev 

411675300001 03 


1 


1 

2 

1 

2

5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

W/S=16/12/12/16 mils W=12 mils 

 

 

 

B 

1 1 


Title 

Size 

Document 

Number 

Rev 


HDD_LED# 

C_SD_D8 

C_SINTRQ 

C_SD_D9 

C_SD_D10 

C_SDCS3# 

C_SD_D5 

C_SD_D0 

C_SD_D12 

C_SDA2 

C_SD_D15 

C_SD_D13 

C_SDA1 

C_SD_D1 

C_SD_D2 

C_SDDREQ 

C_SD_D4 

C_SDDACK# 

C_SDA0 

C_SIORDY 

C_SDIOW# 

C_SD_D6 

C_SD_D14 

A15_A2 

C_SD_D3 

C_SDIOR# 

C_SD_D11 

C_SDCS1# 

C_SD_D7 

B26_B12 

C_RSTDRV2# 

A26_B3 

B26_B12 

A26_B3 

A15_A2 

C_RSTDRV2# 

C_SD_D5 

C_SD_D0 

C_SD_D2 

C_SD_D4 

C_SD_D6 

C_SD_D1 

C_SD_D3 

C_SD_D7 

C_SD_D10 

C_SD_D9 

C_SD_D12 

C_SD_D11 

C_SD_D14 

C_SD_D8 

C_SD_D15 

C_SD_D13 

C_SDDREQ 

C_SDIOW# 

C_SDIOR# 

C_SIORDY 

C_SDDACK# 

C_SINTRQ 

C_SDA1 

C_SDA0 

C_SDCS1# 

HDD_LED# 

C_SDCS3# 

C_SDA2 

GND 

+5V 

+5V 

GND 

GND GND 

GND 

+5V 

+5V 

GND 

GND 

R1 

5.6K 

1 2 

J1 

HDR/MA/26PX2/1MM 

HIROSE 

FX5-52S2A-SVL 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

A17 

A18 

A19 

A20 

A21 

A22 

A23 

A24 

A25 

A26 

B1 

B2 

B3 

B4 

B5 

B6 

B7 

B8 

B9 

B10 

B11 

B12 

B13 

B14 

B15 

B16 

B17 

B18 

B19 

B20 

B21 

B22 

B23 

B24 

B25 

B26 

FD1 

1 

FD501 

1 

MTG2 

ID2.2/OD5.0 

1 

MTG1 

ID2.2/OD5.0 

1 

R2 470 

0603 

1 2 

J2 

HDR/FM/22PX2/2MM 

SPEED 

B066-44X2-009 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

W/S=16/12/12/16 mils W=12 mils 

 

 

 

B 

1 1 


Title 

Size 

Document 

Number 

Rev 


HDD_LED# 

C_SD_D8 

C_SINTRQ 

C_SD_D9 

C_SD_D10 

C_SDCS3# 

C_SD_D5 

C_SD_D0 

C_SD_D12 

C_SDA2 

C_SD_D15 

C_SD_D13 

C_SDA1 

C_SD_D1 

C_SD_D2 

C_SDDREQ 

C_SD_D4 

C_SDDACK# 

C_SDA0 

C_SIORDY 

C_SDIOW# 

C_SD_D6 

C_SD_D14 

A15_A2 

C_SD_D3 

C_SDIOR# 

C_SD_D11 

C_SDCS1# 

C_SD_D7 

B26_B12 

C_RSTDRV2# 

A26_B3 

B26_B12 

A26_B3 

A15_A2 

C_RSTDRV2# 

C_SD_D5 

C_SD_D0 

C_SD_D2 

C_SD_D4 

C_SD_D6 

C_SD_D1 

C_SD_D3 

C_SD_D7 

C_SD_D10 

C_SD_D9 

C_SD_D12 

C_SD_D11 

C_SD_D14 

C_SD_D8 

C_SD_D15 

C_SD_D13 

C_SDDREQ 

C_SDIOW# 

C_SDIOR# 

C_SIORDY 

C_SDDACK# 

C_SINTRQ 

C_SDA1 

C_SDA0 

C_SDCS1# 

HDD_LED# 

C_SDCS3# 

C_SDA2 

GND 

+5V 

+5V 

GND 

GND GND 

GND 

+5V 

+5V 

GND 

GND 

R1 

5.6K 

1 2 

J1 


HIROSE 

FX5-52S2A-SVL 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

A17 

A18 

A19 

A20 

A21 

A22 

A23 

A24 

A25 

A26 

B1 

B2 

B3 

B4 

B5 

B6 

B7 

B8 

B9 

B10 

B11 

B12 

B13 

B14 

B15 

B16 

B17 

B18 

B19 

B20 

B21 

B22 

B23 

B24 

B25 

B26 

FD1 

1 

FD501 

1 

MTG2 

ID2.2/OD5.0 

1 

MTG1 

ID2.2/OD5.0 

1 

R2 470 

0603 

1 2 

J2 

HDR/FM/22PX2/2MM 

SPEED 

B066-44X2-009 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

W/S=16/12/12/16 mils W=12 mils 

 

01 

 

C 

1 1 

Monday, December 16, 2002 

Title 

Size 

Document 

Number 

Rev 


CD_LED# 

CDROM_RIGHT 

C_SD_D8 

C_SINTRQ 

C_SD_D9 

C_SD_D10 

C_SDCS3# 

C_SD_D5 

CDROM_COMM 

C_SD_D0 

C_SD_D12 

C_SDA2 

C_SD_D15 

C_SD_D13 

C_SDA1 

C_SD_D1 

C_SD_D2 

C_SDDREQ 

C_SD_D4 

C_SDDACK# 

C_SDA0 

S_CSEL 

C_SIORDY 

C_SDIOW# 

C_SD_D6 

C_SD_D14 

A15_A2 

CDROM_LEFT 

C_SD_D3 

C_SDIOR# 

C_SD_D11 

C_SDCS1# 

C_SD_D7 

C_SD_D3 

CDROM_COMM 

C_SD_D1 

C_RSTDRV2# 

C_SD_D2 

C_SD_D0 

CDROM_LEFT 

C_SD_D5 

C_SD_D6 

C_SD_D4 

C_SD_D7 

CDROM_RIGHT 

C_SD_D10 

C_SDDREQ 

C_SD_D14 

C_SD_D15 

C_SDIOR# 

C_SD_D8 

C_SD_D13 

C_SD_D9 

C_SD_D12 

C_SD_D11 

C_SDCS1# 

C_SIORDY 

C_SDA1 

C_SINTRQ 

CD_LED# 

C_SDIOW# 

C_SDA0 

C_SDA2 

C_SDDACK# 

C_SDCS3# 

S_CSEL 

B26_B12 

C_RSTDRV2# 

A26_B3 

B26_B12 

A26_B3 

A15_A2 

GND 

+5V 

+5V 

GND 

+5V 

+5V 

GND GND 

GND GND 

J1 


HIROSE 

FX5-52S2A-SVL 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

A17 

A18 

A19 

A20 

A21 

A22 

A23 

A24 

A25 

A26 

B1 

B2 

B3 

B4 

B5 

B6 

B7 

B8 

B9 

B10 

B11 

B12 

B13 

B14 

B15 

B16 

B17 

B18 

B19 

B20 

B21 

B22 

B23 

B24 

B25 

B26 

FD1 

1 

J501 

FM/25PX2/ST 

C14301-150XX 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

45 

47 

49 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

46 

48 

50 

GND1 

GND2 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

23 

25 

27 

29 

31 

33 

35 

37 

39 

41 

43 

45 

47 

49 

2 

4 

6 

8 

10 

12 

14 

16 

18 

20 

22 

24 

26 

28 

30 

32 

34 

36 

38 

40 

42 

44 

46 

48 

50 

GND1 

GND2 

FD501 

1 

MTG2 

ID2.2/OD5.0 

1 

MTG1 

ID2.2/OD5.0 

1 


5 

5 

4 

4 

3 

3 

2 

2 

1 

1 

D D 

C C 

B B 

A A 

411675300020 

00 

8080 Finger Print TouchChip Reader BD 

C 

1 1 

Monday, March 10, 2003 

Title 

Size 

Document 

Number 

Rev 


USB_D- 

+5V_USB 

USB_GND 

USB_DM 

USB_DP 

USB_VCC 

USB_DP 

USB_DM 

USB_GND 

USB_VCC 

USB_D+ 

CBL_GND 

WC# 

SDA 

SCL 

OSCIN 

TC_RDB 

OSCOUT 

OSCOUT 

OSCIN 

TC_WRB 

TC_NRST 

TC_CSB 

TC_INT 

TC_A0 

DATA0 

DATA1 

DATA2 

DATA3 

DATA4 

DATA5 

DATA6 

DATA7 

TC_PWR_CNTL 

IDD_SENSE 

DATA2 

DATA4 

DATA1 

DATA7 

DATA6 

DATA0 

DATA3 

DATA5 

TC_INT 

TC_CSB 

TC_RDB 

TC_NRST 

TC_WRB 

IDD_SENSE 

TC_PWR_CNTL 

WC# 

SDA 

SCL 

TC_A0 

PAD_SEL0 

GND 

VCC 

GND GND GND GND 

GND 

VCC 

GND 

GND GND 

VCC 

GND 

GND 

VCC 

GND 

VCC 

GND 

GND GND 

J1 

HDR/MA-5 

ACES 

87152-0507 

1 

2 

3 

4 

5 

J2 

HDR/MA-20 

ACES 

87152-2002 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

C5 

0.1U 

50V 

0603 

1 

2 

D 

S G 

Q1 

SI2301DS 

G 

D 

S 

R5 

10K 0603 

1 2 

L4 

120Z/100M 1608 

1 2 

R6 10 

0805 

1 2 

C2 

0.1U 

50V 

0603 

1 

2 

C10 

33P 

0603 

50V 

1 

2 

R1 

4.7K 

0603 

1 

2 

R4 

47K 

0603 

1 

2 

L6 

120Z/100M 

1608 

1 2 

C1 

1U 

0603 

1 

2 

R3 

1.5K 

0603 

1 

2 

L3 

120Z/100M 1608 

1 2 

L5 

120Z/100M 

2012 

1 2 

L1 

120Z/100M 

1608 

1 

2 

MTG1 

ID2.2/OD6.5 

1 

R2 

4.7K 

0603 

1 

2 

C11 

33P 

0603 

50V 

1 

2 

C7 

0.1U 

50V 

0603 

1 

2 

C3 

22P 

0603 

1 

2 

U2 

ST92163 

PQFP64_0.8MM 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

37 

38 

39 

40 

41 

42 

43 

44 

60 

61 

62 

63 

64 

25 

26 

27 

28 

29 

30 

31 

34 

17 

21 

22 

23 

24 

35 

36 

45 

46 

47 

50 

51 

56 

57 

55 

54 

53 

52 

32 

33 

48 

49 

58 

59 

20 

19 

18 

16 

15 

14 

13 

12 

WKUP14/A10/P1.2 

WKUP14/A9/P1.1 

WKUP14/A8/P1.0 

D7/A7/P0.7 

D6/A6/P0.6 

D5/A5/P0.5 

D4/A4/P0.4 

D3/A3/P0.3 

D2/A2/P0.2 

D1/A1/P0.1 

D0/A0/P0.0 

SDS/INT7/P3.7 

AS/INT7/P3.6 

SIN/INT7/P3.5 

DCD/INT7/P3.4 

RXCLK/INT7/P3.3 

CLKOUT/TXCLK/INT7/P3.2 

RTS/INT7/P3.1 

SOUT/INT7/P3.0 

WKUP14/A15/P1.7 

WKUP14/A14/P1.6 

WKUP14/A13/P1.5 

WKUP14/A12/P1.4 

WKUP14/A11/P1.3 

WDOUT/NMI/P5.7 

WKUP9/TOUTB/P5.6 

EW/WDIN/INT0/P5.5 

USBOE/WKUP8/P5.4 

TOUTA/INT2/P5.3 

INT3/P5.2 

TINB/INT4/P5.1 

TINA/INT1/P5.0 

AVDD 

VDD_0 

OSCIN 

VSS_0 

OSCOUT 

RESET 

VPP 

DS 

USBGND 

USBVCC 

USBDP0 

USBDM0 

VDD_1 

VSS_1 

BREQ/P4.0 

WAIT/P4.1 

P4.2 

BACK/P4.3 

NC_0 

NC_1 

NC_2 

NC_3 

NC_4 

NC_5 

WKUP10/SDA/INT5/P6.0 

WKUP11/SCL/EXTRG/INT6/P6.1 

WKUP12/AIN0/INTCLK/P6.2 

XTOUT/WKUP13/AIN1/P6.3 

USBSOF/AIN2/P6.4 

USBSOF/AIN3/P6.5 

AIN4/P6.6 

AIN5/P6.7 

L2 

120Z/100M 

1608 

1 

2 

MTG2 

ID2.2/OD6.5 

1 

C6 

0.1U 

50V 

0603 

1 

2 

X1 

8MHZ 

1 2 

R7 

1M/NA 

0603 

1 2 

C9 

0.1U 

50V 

0603 

1 

2 

U1 

AT24C64N 

SO8 

1 

2 

3 

4 

5 

6 

7 

8 

A0 

A1 

A2 

GND 

SDA 

SCLK 

WC- 

VCC 

C4 

22P 

0603 

1 

2 

C8 

1U 

0603 

1 

2 


Reference Material 

Intel Pentium M Processor 

Intel 82855GM Memory Controller Hub (GMCH) 

Intel 82801DBM I/O Controller Hub Mobile (ICH4-M) 

8060 Hardware Engineering Specification 

Intel, INC 

Intel, INC 

Intel, INC 

Technology Corp./MiTAC

SERVICE MANUAL FOR 8080 

Sponsoring Editor : Jesse Jan 

Author : Sissel Diao 

Assistant Editor : Janne Liu 

Publisher : MiTAC International Corp. 

Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C. 

Tel : 886-3-5779250 Fax : 886-3-5781245 

First Edition : May. 2003 

E-mail : Willy.Chen @ mic.com.tw 

Web : http: //www.mitac.com http: //www.mitacservice.com

Mitac 8080 Service Manual - laptop schematics, notebook ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?