Memory Subsystem Architect, Silicon
- linkCopy link
- emailEmail a friend
Google welcomes people with disabilities.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience in ASIC performance power management or low-power design and methodology.
- Experience in computer architecture concepts, such as micro-architecture, cache, pipe-lining, and memory subsystems.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience designing, implementing, or validating in two or more areas such as Coherent fabrics, Caches, Fabrics, IOMMUs, QoS, or Memory Systems.
- Experience in SoC architecture performance analysis, tools, and simulators (e.g., Cycle Accurate, TLM, or Functional).
- Experience with C or C++.
- Experience in SoC system pre-silicon or post-silicon performance analysis and tuning.
- Knowledge of HDL languages such as System Verilog, Verilog.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work with internal stakeholders to define IP, Subsystem and ASIC specifications to meet PPA requirements.
- Collaborate with internal cross-functional teams on pre-silicon performance/power analysis, evaluating design trade-off, writing test and validation plans, and resolving implementation issues.
- Work with cross-functional teams on post-silicon chip bring-ups and on performance, power, and functional issues.
- Perform analysis results in both qualitative and quantitative fields.
- Participate in evaluation of future ASIC designs and general architecture.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.