Engineering Lead, Physical Design Flow, Silicon
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Minimum qualifications:
- Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience.
- 8 years of experience with EDA tool workflows in semiconductor environments.
- Experience with scripting languages (e.g., Python, Bash, Tcl) for workflow automation and data visualization.
- Experience developing and supporting ASIC physical design flows, methodologies in process nodes, ASIC physical design, physical design flows, and methodologies.
- Experience with physical design processes (e.g., EDA tools, RTL to GDS workflows, developing checkers, and workflow auditing tools).
Preferred qualifications:
- Experience in extraction of ASIC design parameters, QOR metrics, and analyzing trends.
- Experience with closing blocks with multiple power regions with low power focus.
- Expertise in one or more aspects of physical design implementation, including 2.5D and 3DIC integration and signoff, IP integration, chip finishing issues.
- Proficiency in general software engineering principles (data structures, algorithms, profiling, optimization) and Object Oriented Programming languages such as C++.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Develop, support, and execute implementation flows from RTL through GDS including some or all of the following: Synthesis, Floorplanning, Place and Route, Power/Clock Distribution, Extraction, etc.
- Collaborate with the central cad team to implement flows and methodologies to improve Performance, Power and Area (PPA) and Turn-Around-Time (TAT).
- Work with EDA vendors to resolve tool issues and bugs.
- Own and drive execution of Place and Route block during execution phase.
- Remove roadblocks for engineers in Auto Place and Route (APR) activities.
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