Senior Design Verification Engineer, Mixed Signal, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience developing and maintaining verification testbenches, test cases, and test environments.
Preferred qualifications:
- Experience in one or more scripting languages (e.g., Python, etc.).
- Experience with RTL, low power (e.g., UPF/CPF), gate level (e.g., GLS) and formal verification techniques.
- Experience creating/using verification components and environments in methodology (e.g., UVM, VMM, OVM).
- Experience working with mixed signal (e.g., AMS/DMS) designs and mixed mode verification.
- Experience in writing SystemVerilog models of analog blocks using advanced techniques (e.g., Real Number Modeling (RNM), Verilog-AMS, etc.).
- Experience in creating detailed block-level design verification strategies and plans.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.Responsibilities
- Plan and execute on the verification of digital and mixed signal design blocks by understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Identify and implement key coverage metrics for stimulus and corner-cases to identify verification holes and to show progress towards tape-out.
- Work with design verification and other stakeholders to come up with detailed execution plans, schedule, dependencies, and deliverables.
- Work with system, software, design, and physical implementation stakeholders to make technical decisions.
- Be the primary point of contact for functional verification for cross-functional teams and lead/drive the building of reusable Design Verification (DV) infrastructure components.
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