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RTL Design Lead, Silicon

GoogleBengaluru, Karnataka, India

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with digital design in ASIC.
  • 4 years of experience in people management.
  • Experience with RTL design using Verilog/System Verilog and microarchitecture.
  • Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred qualifications:

  • Master’s degree in Electrical Engineering or Computer Engineering.
  • Experience with methodologies for low power estimation, timing closure, and synthesis.
  • Experience leading IP/SoC design team for low power SoCs.
  • Ability to drive a multi-generational roadmap for IP/SoC development.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

  • Lead a team that delivers fabric interconnect IP, platforms, and subsystems.
  • Drive multi-generation roadmap for design optimization.
  • Define micro-architecture details (e.g., interface protocol, block diagram, data flow, pipelines, etc.).
  • Oversee RTL development, debug functional, and performance simulations.
  • Participate in synthesis, timing/power estimation, and Field-Programmable Gate Array/silicon bring-up.

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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