Physical Design Engineer, Static Timing Analysis
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 5 years of experience in static timing (i.e., to create full chip timing constraints, perform full chip static timing analysis and timing ECO creation).
- Experience in working across various physical design areas (i.e., EDA scripting, block level synthesis, floorplanning, place and route, and congestion mitigating utilizing standard EDA tools).
- Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.
Preferred qualifications:
- 12 years of experience in the domain of physical design and static timing analysis.
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
- Experience in full chip design planning and working with multiple foundries.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Knowledge of semiconductor device physics and transistor characteristics.
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Create complex TCL timing constraints.
- Perform full chip static timing analysis, timing ECO creation, and final timing sign-off for ASIC tape outs.
- Perform block level synthesis, floorplanning, and place and route.
- Utilize Perl, Python, Tcl, and Bash to create flow automation scripts.
- Own and maintain Primetime STA flows.
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