Physical Design Lead, Silicon, Google Cloud
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Minimum qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 15 years of experience in ASIC design implementation flows.
- Experience in driving execution for low-power physical design implementation with industry standard synthesis and Static Timing Analysis (STA) tools.
- Experience in sign-off convergence including STA, electrical checks, and physical verification.
Preferred qualifications:
- 5 years of experience with CPUs and leading processor Physical Design teams.
- Experience in programming and scripting languages such as Python, TCL, or Perl.
- Experience with metric driven Performance Power Area (PPA).
- Experience in CPU implementation, including critical timing and power fix iterations with RTL and Micro architecture teams.
About the job
In this role, you will be part of a team developing cutting-edge ASICs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power, and area in mind.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Drive industry leading high-performance and low power design implementation for advanced CPUs.
- Manage block and physical implementation and Quality of Results (QoR) (e.g., power, timing, area).
- Collaborate with RTL design, cross-site Physical Design, and CAD teams on micro architectural critical items for timing and power convergence.
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