Design Verification Engineer, Multimedia, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 2 years of experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for ASICs.
- Experience verifying digital systems using standard IP components/interconnects (i.e., microprocessor cores and hierarchical memory subsystems).
- Experience with object oriented programming.
Preferred qualifications:
- Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
- Experience with image processing or other multimedia IPs such as display or video codec.
- Experience with ASIC standard interfaces and memory system architecture.
- Experience with performance verification of ASICs and ASIC components.
- Experience with emulation platforms
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out and align methodology across different groups globally.
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