CPU Design Verification Engineer, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- Experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.
- Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
- Experience creating and using verification components and environments in standard verification methodology.
Preferred qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience with UVM, SystemVerilog, or other scripting languages (e.g. Python, Perl, Shell, Bash, etc.).
- Familiar with CPU implementation, assembly language, or compute SOCs.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Lead coverage measures to identify verification holes and to show progress towards tape-out.
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